Core field isolation for a NAND flash memory

Details Core field isolation for a NAND flash memory Core field isolation for a NAND flash memory

1999-05-11

2001-05-08

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Utilizing varying dielectric thickness

C438S258000, C257S326000

Reexamination Certificate

active

06228782

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a memory device on a semiconductor substrate. The present invention has particular applicability in manufacturing nonvolatile semiconductor memory devices having high quality field isolation.
BACKGROUND ART
Conventional nonvolatile semiconductor memories, such as flash electrically erasable programmable read only memories (flash EEPROMs), typically comprise a floating gate memory cell, which includes a source region, a drain region and a channel region formed in a semiconductor substrate, and a floating gate formed above the substrate between the channel region and a control gate. A voltage differential is created in the cell when a high voltage is applied to the control gate while the channel region is kept at a low voltage, causing injection of electrons from the channel region into the floating gate, as by tunneling, thereby charging the floating gate. This movement of electrons is referred to as programming, and the high voltage (i.e., about 18 volts) applied to the control gate is known as program voltage.
A typical architecture for a flash memory system, referred to as a NAND architecture, is depicted in FIG.
1
. The NAND architecture includes several strings
110
, known as NAND strings, of floating gate memory transistors (or “memory cells”)
120
, each transistor
120
coupled to the next transistor
120
in the string
110
by coupling the source
121
of one transistor
120
to the drain
122
of the next transistor
120
. At either end of each string
110
is a selection transistor, one of which is referred to as a select drain transistor
130
, and the other of which is referred to as a select source transistor
140
. Each NAND string
110
and its associated pair of selection transistors
130
,
140
is known as a bit line BL
1
-BLn. A plurality of word lines WL
1
-WLm, perpendicular to the NAND strings
110
, each connect to the control gate
123
of one memory cell
120
of each NAND string
110
. A line SELD connects the gates of the select drain transistors
130
, and a line SELS connects the gates of the select source transistors
140
. Peripheral devices, such as power transistors (not shown) supply voltages of up to
23
volts for programming and other functions of the memory system.
FIG. 2A
depicts a typical floating gate memory cell
120
, which includes source/drain regions
220
and channel region
230
formed in substrate
210
, such as by implantation of impurities, tunnel oxide
240
of about 95 Å, polysilicon floating gate
250
, dielectric layer
260
and polysilicon control gate
270
.
FIG. 2B
depicts a typical selection transistor
130
,
140
, which includes source/drain regions
221
and channel region
231
formed in substrate
210
, as by implantation of impurities, and gate oxide
241
of about 180 Å. Polysilicon floating gate
250
, dielectric layer
260
and polysilicon control gate
270
are formed simultaneously with the corresponding parts of the floating gate memory cells
120
. Floating gate
350
and control gate
270
are then short circuited together by contact
280
to form the selection transistor's gate
290
.
The NAND flash memory system described above is typically manufactured on semiconductor substrate
210
as illustrated in
FIGS. 3A-3C
. Initially, as depicted in
FIG. 3B
, field isolation regions
310
,
330
are formed, as by local oxidation of silicon (LOCOS), for the memory core (i.e., the array of memory cells
120
and selection transistors
130
,
140
which will be formed in core channel areas
320
), and for peripheral circuitry, which will be formed in areas
321
. As shown in
FIG. 3A
, the core field oxide regions
310
are typically formed as parallel rows separated by channel areas
320
. Core field oxide
310
typically has a thickness of about 2000 Å to about 3000 Å to achieve small memory cell size and maintain the integrity of tunnel oxide
240
. A thicker field oxide
330
of about 4000 Å to about 6000 Å is typically used in the peripheral circuit area to meet the high voltage isolation and gate oxide reliability requirements of the peripheral devices.
The current demands for miniaturization into the deep submicron range for increased circuit density require optimization of memory cell isolation and peripheral circuit isolation to maintain the performance of the flash memory system. Due to the different thicknesses of the core field oxide
310
and the peripheral field oxide
330
, optimization of the field isolation is complex. Peripheral field isolation is typically achieved by performing a high-energy boron implant B
1
(e.g., about 5×10
12
atoms cm
−2
at about 120-180 keV) through the field oxide
310
,
330
after a mask
340
is formed over portions of substrate
210
, to implant the dopant into substrate
210
immediately below the peripheral field oxide
330
(see plus signs representing dopant). However, this single high-energy implant is not suitable for optimizing isolation of both the flash memory core and its peripheral circuitry, since the impurities are driven too far into the substrate under the thinner core field oxide
310
to sufficiently enhance isolation, as depicted at the left side of FIG.
3
B. Thus, a separate implantation step must be performed to optimize the core field isolation. As shown in
FIG. 3C
, after gates
240
,
241
are formed, and a polysilicon layer
350
(used to form gate
250
in core transistors
120
,
130
,
140
) has been deposited, masked by mask
360
, and etched, an implant B
2
, such as boron at about 10
13
atoms cm
−2
and about 80 keV, called a “channel stop implant”, is introduced into the core region immediately below core field oxide
310
to optimize core field isolation.
Referring again to
FIG. 1
, in the operation of a NAND flash memory, a problem arises when it is desired to program one selected cell S on a word line without programming other cells on the same word line. When program voltage Vprog is applied to a word line such as WL
2
, that voltage is applied not only to the selected cell S but also to the cells along the same word line which are unselected for programming. An unselected cell U on the word line, especially a cell adjacent to the selected cell S, may become inadvertently programmed. The unintentional programming of an unselected cell in a selected word line is referred to as “program disturb”.
A well-known technique called “self-boosting” is typically employed to prevent program disturb, wherein the unselected bit lines BL
2
-BLn are electrically isolated and a pass voltage Vpass, such as about 10 volts, is applied to the unselected word lines WL
1
, WL
3
-WLm during programming. The unselected word lines capacitively couple to the unselected bit lines, causing a voltage Vboost, such as about 8 volts, to exist on the unselected bit lines, which tends to lower the voltage across the tunnel oxide and, hence, reduce program disturb.
The efficiency of the self-boosting technique (i.e., the value of Vboost) is directly related to the doping profile of the core memory cell channel regions; i.e., the portion of channel areas
320
between the core field oxide
310
on which floating gate memory cells
120
are formed. Boosting efficiency is enhanced if memory cell channel areas
320
are lightly and shallowly doped, and boosting efficiency is decreased if memory cell channel areas
320
are heavily and deeply doped. Disadvantageously, the conventional blanket high-energy implant B
1
employed to optimize the peripheral field isolation results in the entirety of core channel areas
320
being deeply and heavily doped, which significantly reduces boosting efficiency by allowing current leakage to occur between bit lines. This tends to increase program disturb, thereby degrading the performance and reliability of the finished device.
There exists a need for a NAND flash memory methodology enabling optimization of core and peripheral field isolations without unduly degrading self-boosting

Affiliated with

Also associated with

Rating

Core field isolation for a NAND flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Core field isolation for a NAND flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Core field isolation for a NAND flash memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2447722