Core clock correction in a 2/N mode clocking scheme

Details Core clock correction in a 2/N mode clocking scheme Core clock correction in a 2/N mode clocking scheme

1998-10-13

2001-03-27

Wambach, Margaret R. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S142000, C327S144000, C327S147000

Reexamination Certificate

active

06208180

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of clock generation; more particularly, the present invention relates to generating bus clock signals and core clock signals, such as those having a 2/N ratio relationship with respect to each other.
BACKGROUND OF THE INVENTION
Historically the system frequency of a computer was limited by the available silicon technology. In other words, system board technology was capable of higher frequency operation than that of microprocessors provided by then available silicon technology. Computer systems designed using older technologies commonly operated both the system board and the microprocessor at the lower frequency required by the microprocessor. However, because silicon technology has advanced more rapidly over time than system board technology, a crossover has occurred. Today, advanced silicon technology provides microprocessors that are capable of operating at much higher frequencies than currently available system boards.
Besides system board and microprocessor technologies, other situations exist where differing technology constraints may result in distinct frequency domains. For example, a microprocessor and a cache memory may be manufactured using different silicon technologies, each technology providing a different maximum frequency of operation. A microprocessor and a floating point unit may also be operated advantageously at different frequencies. In these examples, the cache memory and/or floating point unit may be either on the same chip (or die) as the CPU, or on a separate chip. Even when manufactured on the same chip, individual functional blocks that exchange data may be advantageously operated at a different frequencies. Other examples of devices that may be advantageously operated at different frequencies are discrete logic components and telecommunications devices.
Today, in order to provide high performance computer systems, it is advantageous to operate the microprocessor(s) at its highest possible frequency and other parts of the computer system at a lower frequency dictated by either system board technology or other technology constraints. Transferring data between various components that operate at different frequencies may be synchronous or asynchronous.
Synchronous designs in microprocessors are advantageous over asynchronous designs for several reasons. First, microprocessor design validation tools are optimized for debugging synchronous logic designs. Using synchronous design techniques makes microprocessor design and validation much easier and more reliable. Second, synchronous designs are mandated in fault tolerant computer systems that use a master-checker scheme. In a master-checker system a first processor, the master, operates lock-stepped with a second processor, the checker. During each clock cycle, the checker processor monitors whether the two processors produce identical results on their pins to provide error checking. Because asynchronous data transfer designs do not provide the requisite lock-stepped operation they are not acceptable in master-checker systems.
Some microprocessors operate internally at an integer multiple of the frequency of the computer system bus. In such a computer system, synchronous data transfer between components operating at different frequencies is facilitated by the fact that a data transfer edge of the lower frequency clock corresponds to a data transfer edge of the higher frequency clock. Therefore, the data transfer edge of the lower frequency clock (and/or corresponding data transfer edges of the higher frequency clock) can be used to cause data transfer. However, integer multiple frequency designs only take advantage of quantum-leap improvements in silicon technology. For example, if system board technology is limited to 50 MHz operation, then microprocessors operating at 100, 150, 200, . . . MHz can be used in an integer multiple design. Suppose that currently available silicon technology provides microprocessors capable of operating at 120 MHz. The additional 20% performance beyond 100 MHz is not utilized in an integer multiple design. It would be advantageous to provide a microprocessor design capable of operating at more flexible frequency ratios to the system bus while also providing synchronous data transfer between the microprocessor and other devices on the computer system bus. In general, it would be advantageous to provide synchronous data transfer between a variety of digital logic and memory devices that operate according to flexible operational frequency ratios. The present invention provides these advantageous results.
One prior art 1/N mode bus clock generation scheme supports 1/N ratio bus clock to core clock, where N is limited to being 2, 3, or 4. In 1/N mode clock scheme, a phase-locked loop (PLL) generates a core clock signal which is at N times higher frequency than the system clock received by the integrated circuit. A programmable ring counter generates an enable signal every Nth cycle which selects every Nth cycle of the core clock to generate the internal bus clock signal.
One advantage of such a scheme is that the core clock and bus clock share the same clock distribution network for many stages. This greatly reduces the possible skew between the core clock and the bus clock. In fact, the skew between the bus clock and the core clock is no worse than the intra-unit skew between core clocks. Thus, it is desirable to have a single clock distribution path for both the core clock and the bus clock, is particularly advantageous, allowing easy management of the skew between the two clocks.
At least one prior art microprocessor uses a phased locked loop (PLL) with some extra logic to generate a 2/3 mode clock. Although this uses the same PLL for bus clocks and core clocks, there is a separate clock distribution path for the two clocks.
Therefore, a system, method, and apparatus for synchronous data transmission between digital devices operating at frequencies having a 2/N integer ratio relationship is needed.
SUMMARY OF THE INVENTION
The present invention provides a clock generator fabricated on an integrated circuit is described. In one embodiment, the clock generator comprises a core clock generator configured to generate a core clock signal, a bus enable generation logic configured to generate first and second bus clock enable indications. A first circuitry is configured to generate a bus clock signal by selecting every N/2 cycles of the core clock signal in response to the first and second bus clock enable indications. In one embodiment, N is not an integer greater than 2. The clock generator also includes a detector that is configured to determine whether the core clock signal is out of phase with the bus clock signal and correction circuitry that places the core clock signal in phase with a bus clock signal if the detector determines that the core clock signal is out of phase with the bus clock signal.


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