Core array and periphery isolation technique

Details Core array and periphery isolation technique Core array and periphery isolation technique

1998-01-20

1999-12-21

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438424, 438296, 438444, H01L 2176

Patent

active

06004862&

ABSTRACT:
A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to the core area, comprising the steps of: forming a first layer of first insulator material above a semiconductor substrate having a core area and a periphery area, wherein the first insulator material constitutes a polish stop for polishing processes and also as an oxidation barrier; patterning the first layer of first insulator material to expose first portions of the semiconductor substrate substantially only in the core area while using the first insulator material to substantially mask the periphery area; forming a plurality of trenches into the exposed first portions of semiconductor substrate in the core area; filling the plurality of trenches with an insulator; polishing down to the first layer of first insulator material; removing the first layer of first insulator material; forming a second layer of first insulator material over the core and periphery areas; forming openings down into the second layer of first insulator material to expose second portions of the semiconductor substrate substantially only in the periphery area while using the second layer to substantially mask the core area; and forming an isolation region in the exposed second portions of the semiconductor substrate.

REFERENCES:
patent: 4944836 (1990-07-01), Beyer et al.
patent: 5084071 (1992-01-01), Nenadic et al.
patent: 5712205 (1998-01-01), Park et al.
patent: 5728620 (1998-03-01), Park
patent: 5858830 (1999-01-01), Yoo et al.

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