Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Patent
1996-03-20
1999-12-21
Maung, Zarni
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
345503, 463 45, G06F 1500
Patent
active
06006319&
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a co-processor system and an external memory unit with an auxiliary processing function. More specifically, the present invention relates to a co-processor system and an external memory unit with an auxiliary processing function, in which a program is stored in a memory of the external memory unit which is detachably attached to an information processing apparatus such as a gaming machine and an image processing apparatus, and a processor provided in the external memory unit cooperates with a processor provided in the information processing apparatus.
2. Related Art
One example of such a kind of co-processor system is disclosed in, for example, Japanese Patent Application Laying-open No. 6-790093 laid-open on Mar. 22, 1994. In brief, this prior art is a system in which a CPU 1 within a main unit of an information processing apparatus and a further CPU 2 called a "Mario chip" access a program in a ROM 3 as shown in FIG. 1, and the CPU 1 executes information processings according to the program. In the prior art, the program for operating the CPU 1 is transferred from the ROM 3 to a RAM 4 and stored therein (down-loaded). Thereafter, the CPU 1 indirectly executes the program of the ROM 3 by directly accessing the program being transferred into the RAM 4. On the other hand, the Mario chip 2 directly accesses the ROM 3 to execute the program in a period that no data is transferred to the RAM 4, i.e., a period that the ROM 3 is not accessed by the CPU 1.
Furthermore, a parallel processing apparatus shown in FIG. 2 can be regarded as a kind of co-processsor system; however, in a case of FIG. 2 system, a first CPU 6a and a second CPU 6b are switched by a bus controller 5 to be connected to a ROM 7 in a time-sharing manner, whereby a necessary program is down-loaded from the ROM 7 to a first RAM 8a or a second RAM 8b. A common clock from a clock generator 9 is applied to the CPU 6a and the CPU 6b. Then, the CPU 6a or the CPU 6b individually and simultaneously or synchronously executes the program stored in the RAM 8a or the RAM 8b on the basis of the same clock. That is, in FIG. 2 system, the both CPUs 6a and 6b do not execute the program of the ROM 7 by directly accessing the ROM 7 in the same machine cycle period, and the program is transferred to the RAMs 8a and 8b corresponding to the CPUs 6a and 6b, and then, the CPUs 6a and 6b directly access the RAMs 8a and 8b, and therefore, the both CPUs 6a and 6b do not directly access the ROM 7 in the same operation cycle period.
In FIG. 1 prior art, the ROM 3 is occupied by the Mario chip 2 when the Mario chip 2 is to be operated. Thus, if it is required that the CPU 1 and the Mario chip 2 are to be simultaneously operated, it becomes necessary to provide a further memory such as the RAM 4. Therefore, in preparing a program, there are many operational limitations or restrictions. For example, (1) it is necessary to prepare programs individually for the CPU 1 and the Mario chip 2 on the basis of architectures suitable for the CPU 1 and the Mario chip 2. (2) If the program for the CPU 1 is to be incorporated within the ROM 3, as described above, the program must be down-loaded, and therefore, it is necessary to write the program in a series of ROM addresses. (3) If a capacity of the RAM 4 is low, the program necessary for the CPU 1 can not be loaded in whole, and therefore, it becomes necessary to divide the program into divided program blocks and to down-load respective divided program blocks. In case (3), it is necessary to write jump programs or sub-routine programs for each of the respective divided program blocks, and even if the same sub-routine program is to be used for the respective divided program block, the same sub-routine program must be prepared for each of the respective divided program blocks, and accordingly, much of the capacity of the ROM is wasted.
In FIG. 2 prior art, there is also the problem (3) of the above described FIG. 1 prior art, and in addition thereto, t
REFERENCES:
patent: 4089524 (1978-05-01), Hauck
patent: 4777621 (1988-10-01), Miner et al.
patent: 5103499 (1992-04-01), Miner et al.
patent: 5283902 (1994-02-01), Dorn
patent: 5357604 (1994-10-01), San et al.
patent: 5388841 (1995-02-01), San et al.
patent: 5395112 (1995-03-01), Darling
patent: 5471607 (1995-11-01), Garde
patent: 5551045 (1996-08-01), Kawamoto et al.
patent: 5594473 (1997-01-01), Miner et al.
patent: 5599232 (1997-02-01), Darling
patent: 5680534 (1997-10-01), Yamato et al.
patent: 5685005 (1997-11-01), Garde et al.
patent: 5691493 (1997-11-01), Usami et al.
patent: 5787488 (1998-07-01), Garde
patent: 5802376 (1998-09-01), DeRoo et al.
patent: 5850230 (1998-12-01), San et al.
Synchronized Dual 8051 Shared RAM System, IBM Technical Disclosure Bulletin, vol. 30, No. 5, Oct. 1987, pp. 163-72.
Bradly K. Fawcett, The Z8000 Microprocessor: A Design Handbook, Prentice-Hall, 1982, Ch. 6, Jul. 1983.
Takahashi Toyofumi
Tanaka Toshio
Terakawa Hideaki
Caldwell Andrew
Creative Design Inc.
Maung Zarni
Nintendo Co. Ltd.
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