Electrical computers and digital processing systems: processing – Architecture based instruction processing
Reexamination Certificate
1998-05-27
2001-06-12
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
C712S034000
Reexamination Certificate
active
06247113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of data processing. More particularly, this invention relates to data processing systems incorporating coprocessors.
2. Description of the Prior Art
It is known to provide data processing systems incorporating both main processors and a coprocessor. In some systems it is known to be able to provide one or more different coprocessors with a main processor. In this case, the different coprocessors can be distinguished by different coprocessor numbers. A coprocessor instruction encountered in the instruction data stream of the main processor is issued on a bus coupled to the coprocessor. The one or more coprocessors (that each have an associated hardwired coprocessor number) attached to the bus examine the coprocessor number field of the instruction to determine whether or not they are the target coprocessor for that instruction. If they are the target coprocessor, then they issue an accept signal to the main processor. If the main processor does not receive an accept signal, then it can enter an exception state to deal with the undefined instruction.
Given that the coprocessor instructions are a subset of the main processor instructions, in many circumstances instruction bit space is limited for the coprocessor. These problems are made worse if the coprocessor requires a rich instruction set with a large number of wide operations (e.g. wide resister fields needed to cope with the provision of a large number of registers within the coprocessor). A further complication is that the coprocessor may manipulate multiple different types of data and an indication of data type needs to be passed to the coprocessor within the coprocessor instruction.
SUMMARY OF THE INVENTION
It is an object of the present invention to address the problems of limited instruction bit space for coprocessors.
Viewed from one aspect the present invention provides an apparatus for processing data, said apparatus comprising:
a main processor for performing data processing in response to a stream of data processing instructions, said data processing instructions including at least one coprocessor instruction that has:
an opcode specifying a data processing operation to be performed by a coprocessor; and
a coprocessor identification field for identifying a target coprocessor for said coprocessor instruction; wherein
at least one bit of said coprocessor identification field also serves as a data type field indicating a data type to be used in said data processing operation;
a coprocessor coupled to said main processor by a bus, said main processor being responsive to a coprocessor instruction to issue at least a representation of said coprocessor instruction upon said bus and said coprocessor being responsive to said coprocessor instruction upon said bus to compare said coprocessor identification field with at least one coprocessor number value identifying said coprocessor and to issue an accept signal to said main processor via said bus if said coprocessor is said target processor; wherein
if said coprocessor is a multiple data type coprocessor that supports multiple data types, then it has multiple coprocessor number values, issues an accept signal for any of said multiple coprocessor number values and uses said data type field to control the data type used.
The present invention recognises and exploits that the coprocessor number can be made to serve a dual function of identifying a target coprocessor for a coprocessor instruction and specifying to a coprocessor which data type it should use. The frees up coprocessor opcode instruction bit space for other purposes that can then be used to provide a richer instruction set. Furthermore, using the coprocessor number to also carry this data type encoding provide an architecture that may be readily scaled. In particular different coprocessors can be provided that provide a subset or superset of data type support and the main processor address these using the same opcodes with different coprocessor numbers. If the main processor issues a coprocessor instruction of a data type not supported by the coprocessor, then the coprocessor will not accept it and the main processor can use its existing mechanisms to branch to exception handling code to deal with the situation. In embodiments supporting only a single data type, then the coprocessor does not issue an accept signal for any coprocessor number value including a data type field corresponding to an unsupported data type and uses said supported data type independent of said data type field.
A reduced hardware coprocessor can thus be provided without having to have any modifications to support this data type specifying feature and the main processor can deal with the reduced capabilities of the coprocessor using the existing accept or not accept mechanism.
It will be appreciated that coprocessors can support any number of data type between all those that may be specified in the data type field and only a single data type. The coprocessor can achieve this by only accepting coprocessor instructions with a coprocessor number that has the data type field of a supported data type.
A further preferred feature of the invention is that the opcode can be made independent of the data type, which simplifies instruction decoding. In this case the opcode is orthogonal to the data type.
The data type being specified could be various different parameters (e.g. sign encoding type), but is particularly useful to deal with single and double precision data types within a floating point coprocessor.
The main processor may be arranged to stop processing or ignore coprocessor instructions of an unsupported data type, but preferably if said coprocessor does not issue an accept signal due to an unsupported data type being specified by said data type field, then said main processor uses emulation code to emulate said coprocessor instruction for said unsupported data type.
In this way the same code can be run on the main processor at the expense of reduced performance. This may not be a problem if coprocessor instructions of the unsupported data type are rare.
Viewed from another aspect the invention provides a method of processing data with a main processor and a coprocessor, said method comprising the steps of:
performing data processing with said main processor in response to a stream of data processing instructions, said data processing instructions including at least one coprocessor instruction that has:
an opcode specifying a data processing operation to be performed by said coprocessor; and
a coprocessor identification field for identifying a target coprocessor for said coprocessor instruction; wherein
at least one bit of said coprocessor identification field also serves as a data type field indicating a data type to be used in said data processing operation;
in response to a coprocessor instruction, said main processor issuing at least a representation of said coprocessor instruction upon to said coprocessor;
in response to said coprocessor instruction, said coprocessor comparing said coprocessor identification field with at least one coprocessor number value identifying said coprocessor and issuing an accept signal to said main processor if said coprocessor is said target processor; wherein
if said coprocessor is a multiple data type coprocessor that supports multiple data types, then it has multiple coprocessor number values, issues an accept signal for any of said multiple coprocessor number values and uses said data type field to control the data type used.
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An Meng-Al T.
ARM Limited
Nixon & Vanderhye P.C.
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