Coprocessor interface supporting I/O or memory mapped communicat

Details Coprocessor interface supporting I/O or memory mapped communicat Coprocessor interface supporting I/O or memory mapped communicat

1991-06-12

1995-05-30

Eng, David Y.

Boots, shoes, and leggings

3649462, 3649236, 36493149, 3642886, G06G 930, G06F 1516

Patent

active

054209897

ABSTRACT:
A coprocessor 18 comprises a bus controller 24 which further comprises a primary bus controller 28 and a secondary bus controller 30 that drive a floating point processor core 26. The primary bus controller 28 comprises a memory mapped bus interface 32 for processing memory mapped format instructions and an I/O bus interface 34 for processing conventional I/O format instructions. The primary bus controller 28 remains essentially transparent for execution of I/O format instructions and translates memory mapped format instructions into sequential bus cycles compatible to an I/O bus interface for processing conventional I/O format instructions, and for execution by the floating point processor core.

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