Coprocessor instruction format

Details Coprocessor instruction format Coprocessor instruction format

1987-09-18

1991-02-19

Shaaw, Gareth D.

Boots, shoes, and leggings

3642286, G06F 900

Patent

active

049949616

ABSTRACT:
A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

REFERENCES:
patent: 4270167 (1981-05-01), Koehler et al.
patent: 4547849 (1985-10-01), Louie et al.

Affiliated with

Also associated with

Rating

Coprocessor instruction format does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Coprocessor instruction format, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Coprocessor instruction format will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1149015