Coprocessor instruction format

Details Coprocessor instruction format Coprocessor instruction format

1987-09-18

1991-06-04

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 900

Patent

active

050219910

ABSTRACT:
A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

REFERENCES:
patent: 3614745 (1971-10-01), Podvin et al.
patent: 3678467 (1972-07-01), Nussbaum et al.
patent: 3871578 (1975-03-01), Van de Goor et al.
patent: 3970993 (1976-07-01), Finnila
patent: 4101960 (1978-07-01), Stokes et al.
patent: 4149240 (1979-04-01), Mijunas et al.
patent: 4270167 (1981-05-01), Koehler et al.
patent: 4509116 (1985-04-01), Lackey et al.

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