Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-03-27
2004-02-17
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S751000, C257S753000, C257S762000, C438S653000, C438S643000, C438S627000
Reexamination Certificate
active
06693356
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of electronic systems and semiconductor devices, and more specifically to processes in integrated circuit fabrication aiming at reliable multi-level copper metallization.
DESCRIPTION OF THE RELATED ART
In the last few years, copper interconnection has been adapted to silicon integrated circuits due to its low resistance and high electromigration reliability compared to the traditional aluminum interconnection. Single-damascene and dual-damascene methods have been employed for the fabrication of copper interconnection. For multi-level copper interconnects using any of these two methods, improved electromigration reliability, especially improved lifetime of early failures have been reported, for example, in the recent article “A High Reliability Copper Dual-Damascene Interconnection with Direct-Contact Via Structure” (K. Ueno et al, IEEE Internat. Electron Devices Meeting 2000, December 10-13, pp. 265-268). In the technique described, the improvement in multi-level copper circuits has been achieved by making the copper contacts on the bottom of interconnecting vias barrier-free except for an ultra-thin adhesion layer.
In spite of progress such as described in that paper, in known technology many problems still remain related to the copper interconnection concept. For example, the copper traces have to be sealed by barrier layers in order to prevent copper migration into the silicon circuitry where copper atoms are known to offer energy levels for electron recombination/generation, acting as electron life-time killers. The same sealing barriers should protect the porous insulating layers of low dielectric constant (so-called low-k materials) against intruding atoms, which may initiate coalescence of micro-voids into larger voids.
As an additional example, in the preparation process of copper-filled vias, care has to be taken to prepare the via linings so that copper resistivity is prevented from increasing inordinately when the via diameter is shrinking. Some progress in this direction has been described recently in U.S. patent application Ser. No. 90/975,571, filed on Oct. 11, 2001 (Qing-Tang Jiang, “Reducing Copper Line Resistivity by Smoothing Trench and Via Sidewalls”). No attention has been given, however, to practical methods such as whether the via fabrication steps are cost-effective and simple enough for easy clean-up after via preparation.
It has been well documented that grain boundaries, dislocations, and point defects aid the material transport of electromigration (see, for example, S. M. Sze, “VLSI Technology”, McGraw Hill, pp. 409-413, 1988). With the continuing trend of shrinking integrated circuit feature sizes, these unwelcome effects become ever more important, but no techniques have been disclosed for copper metallization to mitigate or avoid these effects.
An urgent need has, therefore, arisen for a coherent, low-cost method of fabricating copper metallizations and copper-filled via interconnections in single and especially dual damascene technology and, simultaneously, improve the degree of component reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
The invention describes the structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.
The barrier deposition and etching method described by the invention is applicable to any dielectric layer, but especially to porous materials of low dielectric constants.
The barrier materials acceptable by the invention include many refractory metals, compounds such as dielectric metal carbides and nitrides, organic dielectric materials, and silicon dioxide. The barrier layers have a thickness in the range from 1 to 50 nm.
The copper-doped transition layer over the barrier layer include materials which provide an electrical resistivity high enough and a current density low enough to suppress electromigration. In some materials, the copper doping exhibits a gradient from low to high, and therefore the resistivity from high to low, from the barrier layer to the copper in the hole. The transition layers have a thickness in the range from 50 to 120 nm.
If the transition layer resistivity can be maintained low enough while still satisfying the basic requirement that copper plating can directly take place on the transition layer, then a copper seed layer deposition will not be necessary. Copper plating can follow right after the copper transition layer deposition.
As a technical advantage of the invention, the transition and barrier layers offer easy chemical clean-up after completing the selective removal process in order to selectively remove the transition and barrier layers from the bottom of the vias.
For the composite structure of a trench-level dielectric and a via-level dielectric, coupled by a middle stop layer, the process step of selectively removing the transition and barrier layers on the bottom of the via comprises a fine-tuned anisotropic plasma etching process. According to the invention, the etch step is designed to remove the (generally horizontal) transition and barrier portions on the bottom of the hole together with the (generally horizontal) transition and barrier portions on the middle stop layer and penetrate only partially into the middle stop layer. Consequently, the remaining stop layer continues to seal the porous dielectric material.
It is an aspect of the invention that the method is fully compatible with dual damascene process flow and deep sub-micron (0.18 &mgr;m and smaller) technologies.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.
REFERENCES:
patent: 6184550 (2001-02-01), Van Buskirk et al.
patent: 6328871 (2001-12-01), Ding et al.
patent: 6551872 (2003-04-01), Cunningham
patent: 6570257 (2003-05-01), Chen et al.
Brennan Kenneth D.
Jiang Qing-Tang
Tsu Robert
Brady III W. James
Everhart Caridad
Lee Calvin
McLarty Peter K.
Telecky , Jr. Frederick J.
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