Compositions – Etching or brightening compositions
Reexamination Certificate
2000-11-16
2004-09-07
Norton, Nadine G (Department: 1765)
Compositions
Etching or brightening compositions
C252S079400, C438S692000
Reexamination Certificate
active
06787061
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the manufacture of integrated circuits, and more particularly to slurries for use in chemical mechanical polishing of copper, copper alloys, and copper diffusion barriers in the formation of interconnect lines on integrated circuits.
2. Background
Advances in semiconductor manufacturing technology have led to the integration of tens, and more recently hundreds, of millions of circuit elements, such as transistors, on a single integrated circuit (IC). To achieve such dramatic increases in the density of circuit components has required semiconductor manufacturers to scale down the size of the circuit elements and the interconnection structures used to connect the circuit elements into functional circuitry, as well as scaling down the spacing between the interconnect.
Manufacturers of integrated circuits have recently shown great interest in replacing conventional aluminum and aluminum alloys with copper to form signal and power interconnections on integrated circuits. Copper interconnect lines have a number of advantages over conventional aluminum-based metallization schemes, including but not limited to, improved electromigration characteristics and lower resistivity per cross-sectional area. These are important attributes that make copper a preferred metallization scheme for manufacturers that continue to shrink the dimensions and line widths of the various elements that make up an integrated circuit.
Copper interconnect on integrated circuits is typically formed by way of a damascene process. This is in contradistinction to aluminum-based interconnections which are typically formed by way of the well-known subtractive etch process. As is known in this field, copper damascene processing involves defining an interconnection by forming trenches in a layer of insulating material having a planarized top surface, depositing a metal, such as copper, over the insulating material and into the trenches. If copper is the metal that is deposited, then a barrier layer that acts to reduce or eliminate the diffusion of copper into the insulating material is typically disposed over the insulating material prior to the deposition of the copper. The damascene process subsequently concludes with the removal of both the copper and barrier layer from the top surface of the insulating material, leaving the metal in the trenches such that these now represent individual interconnect lines.
The removal of the copper referred to above is typically achieved by way of chemical mechanical polishing. However, as the spacing between interconnect lines becomes very small, it has been observed that erosion of the insulating layer is greater in regions where interconnect density is greater. In other words, CMP with a conventional Cu polish has been observed to produce the aforementioned undesirable result of pattern sensitive erosion. This occurs even though many conventional slurries have a high selectivity to the barrier layer or a high selectivity to the oxide dielectric layer. This phenomenon is sometimes referred to as pattern sensitive erosion, the pattern density effect, the geometric effect, or similar expressions.
The non-uniform polishing that occurs due to the pattern density effect is undesirable because, among other things, it makes subsequent planarization operations more difficult, it makes the formation of trenches, and vias from upper interconnect levels more difficult, and it changes the designed for capacitance and resistance characteristics of the interconnect lines which in turns leads to compromised levels of performance and reliability.
What is needed are slurries and methods for polishing copper interconnects on integrated circuits that reduce the magnitude of pattern sensitive erosion of an interlayer dielectric material.
REFERENCES:
patent: 5527423 (1996-06-01), Neville et al.
patent: 5575706 (1996-11-01), Tsai et al.
patent: 5700383 (1997-12-01), Feller et al.
patent: 5728308 (1998-03-01), Muroyama
patent: 5830265 (1998-11-01), Tsang et al.
patent: 5904159 (1999-05-01), Kato et al.
patent: 5954997 (1999-09-01), Kaufman et al.
patent: 6045435 (2000-04-01), Bajaj et al.
patent: 6083419 (2000-07-01), Grumbine et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Norton Nadine G
Umez-Eronini Lynette T.
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