Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal coating
Reexamination Certificate
2002-05-09
2004-10-05
Wong, Edna (Department: 1753)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal coating
C106S001260
Reexamination Certificate
active
06800188
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a copper plating bath and a plating method for substrates using the copper plating bath. More particularly, the present invention relates to a copper plating bath capable of providing a highly reliable copper plating on a substrate such as a silicone wafer semiconductor substrate or printed board having minute circuit patterns and small holes such as blind via-holes, through-holes, and the like, and to a method of copper plating using the copper plating bath.
DESCRIPTION OF BACKGROUND ART
Recently, a build-up method is being applied to mounting circuits for electronic equipment such as cellular phones, personal computers, videos, game machines, and the like. In the build-up method, small holes such as through-holes and via-holes are provided through a laminated board, and metals are deposited in such small holes to allow interconnection among several different circuit layers, whereby multiplayer circuits are fabricated. Of these small holes, metal deposition in via-holes which are minute blind holes (hereinafter referred to as via-holes) is performed by via-hole plating or via-filling.
With via-hole plating, in which a metal film is formed on the side or bottom inside the via-holes, there are difficulties in layering a conductive layer over the holes. In addition, the area of metal film deposition must be increased to guarantee sufficient conductivity between different circuit layers.
On the other hand, the via-filling method in which metals are filled into via-holes can completely fill the holes with the metals and allow other via-holes to be formed on these holes if the via-hole surface is flat after filling. Therefore, this method is very advantageous for downsizing the devices. For this reason, the demand is being shifted from the via-hole plating method, in which insulating materials (insulating layers) can be flattened only with limitation, to the via-filling method in which connecting holes between the layers can be filled.
Conventionally, via-filling is performed by forming holes between an insulating layer and a conductive layer under the insulating layer, forming pillars or posts by electrolytic copper plating, and flattening the surface by removing deposited copper by grinding. Another method comprises activating only the conductive layer in the bottom of the holes by electroless copper plating and selectively piling by electroless copper plating. Still another method is filling holes with a copper paste and the like.
Of these methods, the first method requires grinding of deposited copper plating layers having a substantial thickness, whereas the second method has a drawback of requiring a considerable period of time to obtain a copper plating layer with a desired thickness. The third method is simple, but has a serious problem in terms of reliability. Because this method employs a paste in which metals are dispersed using a solvent and the like, there are problems such as limited conductivity, formation of voids or shrinkage due to a reduction in volume after filling, and peeling of plate from the internal wall of the holes.
For these reasons, a method of completely filling via-holes by electroplating has been proposed in recent years. Plating solutions and plating methods for this purpose have been developed.
However, the plating solutions and plating methods heretofore proposed have the following drawbacks in practical use. Specifically, many proposed plating solutions utilize a mechanism of filling via-holes using a liquid containing a strong leveling component, such as a dye-type leveling component. Such a leveling component exhibits a strong limitation to diffusion and is adsorbed abundantly on the surface with a thin diffusion layer, whereby metal deposition is controlled on that surface, but comparatively accelerated in recessed areas with a thick diffusion layer (i.e. inside via-holes). Via-filling can be achieved in this manner.
However, although this type of plating solution is suitable for a panel plating method for plating the entire surface of the substrates, the leveling component is easily affected by the thickness of the diffusion layer and the flow rate of the plating solution when applied to a substrate in which circuits are previously patterned by a resist or the like or a substrate with both patterns and through-holes. As a result, the metal thickness significantly differs in the center or ends of vias or wires, or a metal may become thick only in the through-hole entrance corners or the one side of the through-hole internal walls, impairing reliability on laminated layers and electric properties.
Although a method of plating using a pulse wave-form has also been proposed, the method not only involves high cost for the facility which results in a high production cost, but also a problem of complicated electric current control.
Furthermore, conventional plating solutions result in difficulty in analysis and control due to inclusion of three or more components as additives. The difficulty in analysis and control impairs dense filling properties, uniformity of film thickness in pattern plating, and maintenance of consistent properties, thereby significantly affecting the yield and cost of the products.
Therefore, development of a technology for highly reliable plating of substrates, particularly those having small holes and minute grooves for wiring, has been desired.
DISCLOSURE OF THE INVENTION
As a result of extensive studies on plating baths for a long period of time to solve the above-described problems, the inventors of the present invention have found that a copper plating bath containing certain components exhibits excellent via-filling characteristics and plating uniformity, can plate co-existing through-holes with superior plating uniformity, and can produce copper plating with high electric reliability on electric circuit boards such as semiconductor wafers having circuits patterns with minute wiring grooves, printed circuit boards, and the like, with an additional advantage of allowing easy analysis of major components of the plating bath.
Specifically, the present invention provides a copper plating bath comprising a reaction condensate of an amine compound and glycidyl ether and/or a quaternary ammonium derivative of this reaction condensate.
The present invention further provides a method of plating a substrate comprising providing a patterned substrate with electro conductivity and plating the substrate using the copper plating bath.
The present invention also provides an additive used for the copper plating bath.
REFERENCES:
patent: 4384930 (1983-05-01), Eckles
patent: 6518182 (2003-02-01), Ishikawa et al.
patent: 2000-273684 (2000-10-01), None
Hagiwara Hideki
Iimura Seiji
Kimizuka Ryoichi
Maruyama Megumi
Miyake Takashi
Ebara-Udylite Co., Ltd.
Wong Edna
LandOfFree
Copper plating bath and plating method for substrate using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Copper plating bath and plating method for substrate using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Copper plating bath and plating method for substrate using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3273963