Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-03-16
2004-10-19
Parekh, Nitin (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S737000, C257S738000, C257S779000, C257S780000, C257S751000, C257S752000, C257S774000, C438S629000, C438S687000, C438S672000
Reexamination Certificate
active
06806578
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits and more particularly to the pads and solder balls used to make electrical connections between the integrated circuit devices having copper wiring and the external electrical environment.
2. Description of the Related Art
Once the manufacturing processes for the last wiring layer of an integrated circuit die is completed, additional processing is required to form connections between the die and its associated printed circuit card or board. This additional processing allows connection to the external electrical environment and is sometimes referred to as “back end of line” or BEOL processing.
One aspect of BEOL processing can involve the formation of lead/tin solder balls, e.g. C4 connections, on the exterior of the integrated circuit die. The solder balls are used to make electrical connection to the last layer of wiring and underlying circuitry contained on the integrated circuit device. In a later assembly process, the free surface of the solder ball is joined to corresponding wiring pads on a printed circuit card, flex circuit cable or ceramic die carrier.
FIG. 1
illustrates a cross section of a conventionally fabricated integrated circuit device having aluminum wiring and solder ball connections. More specifically, the exterior of the integrated circuit has a passivation layer
12
, typically comprised of silicon dioxide, silicon nitride or silicon oxide
itride combinations. The passivation layer
12
covers the aluminum last wiring layer
11
and the passivation layer
12
contains an opening (via hole) that exposes the surface of the last wiring layer. The passivation layer is not planar, but rather conformal to the underlying surface that contains the final wiring layer. The via hole is conventionally formed using a standard lithographic and etching process.
Typically, a pad
13
(e.g., liner/barrier) is formed over the via hole. The pad
13
forms a “transition metallurgy” that provides a robust mechanical connection between the solder ball
14
and both the wiring layer
11
and the passivation layer
12
. The pad
13
also provides low and stable electrical (contact) resistance between the solder ball
14
and the last wiring layer
11
. The pad
13
is typically comprised, for example, of one or more of chromium, tungsten or titanium with overlayers of solderable metals such as copper or gold. Conventionally, the chromium, tungsten, etc. of the pad
13
are placed in contact with the aluminum wiring layer
11
and the solderable metal(s) of the pad
13
is placed in contact with the solder
14
. During solder ball
14
formation on the integrated circuit and subsequent attachment of the solder balls
14
to a printed circuit card, the lead or tin in the solder
14
may completely react with the solderable metal and bring lead or tin into contact with the chromium, tungsten, etc. layer.
In the case of aluminum last wiring layers, there is limited inter-metallic formation between the aluminum
11
and lead and tin in the solder ball
14
. Any tin that diffuses through micro cracks or grain boundaries of the pad
13
does not result in rapid, strong inter-metallic formation with aluminum. Also, with aluminum wiring, there is insufficient reaction to consume the pad
13
, i.e. react it into inter-metallic, or propagate inter-metallic into the aluminum wiring line.
However, high performance integrated circuits have introduced copper as the last wiring layer. Copper has lower electrical resistance than aluminum and, as a result, yields faster propagation of a signal through a wiring line, increasing the operational speed of the integrated circuit. Copper however, readily reacts with (forms inter-metallics with) the tin
14
. The copper-tin inter-metallics have an associated volume change, that can be both mechanically weak and have increased electrical resistance. A mechanically weak inter-metallic can degrade the reliability, e.g. ability to withstand thermal cycles, of the integrated circuit device. The increased electrical resistance of the inter-metallic can also slow the signal propagation both between the device and its external connection and more particularly through internal device wiring.
When sufficient excess of tin exists in the solder ball
14
, as in the case of a solder ball made from eutectic solder (63% tin, 37% lead), inter-metallic formation can be extensive, extending well into the wiring lines degrading signal propagation and potentially damaging dielectric films adjacent to the wires, because of the volume change associated with inter-metallic formation. There is, therefore, a need for an easy to manufacture pad structure which provides mechanically and electrically robust interconnections between copper wiring and solder balls without introducing the possibility of tin or lead diffusion into the last copper wiring lines. The invention described below provides such a pad structure, in a planar configuration.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for forming mechanically and electrically robust interconnections between integrated circuit copper wiring and solder balls, without possibility of tin or lead diffusion from the solder balls into the last copper wiring lines.
One embodiment of the invention comprises a metallurgical structure that includes a passivation layer, a via through the passivation layer extending to a metal line within the metallurgical structure, a barrier layer lining the via, a metal plug in the via above the barrier layer, the metal plug and the metal line comprising a same material, and a solder bump formed on the metal plug.
The “same material” can be copper and the barrier layer can be one or more layers of Ti, TiN, Ta, and TaN. The barrier layer and the metal plug prevent elements within the solder bump from diffusing to the metal line. The metal plug, the barrier layer and the passivation layer form a planar exterior surface of the metallurgical structure. The solder ball can be in direct contact with the metal plug or the structure can include a second barrier layer above the metal plug and a second metal plug above the second barrier layer, where the second metal plug is in direct contact with the solder ball.
Another embodiment of the invention comprises a method of forming an integrated circuit structure that includes forming a via through an exterior of the integrated circuit structure to internal components of the integrated circuit structure, lining the via with a barrier layer, forming a plug above the barrier layer, the plug and the internal components comprising a same material, and forming a connector on the plug.
The “same material” can again comprises copper, and the barrier layer can comprise one or more layers of Ti, TiN, Ta, and TaN. Again, the barrier layer prevents elements within the connector from diffusing to the internal components.
The method also includes a process of polishing the integrated circuit structure such that the plug, the barrier layer and the exterior form a planar surface. The connector can be formed to be in direct contact with the plug or the inventive process can include forming a second barrier layer above the plug and forming a second plug above the second barrier layer, such that the second plug is in direct contact with the connector.
REFERENCES:
patent: 4840302 (1989-06-01), Gardner et al.
patent: 4843453 (1989-06-01), Hooper et al.
patent: 5048744 (1991-09-01), Chang et al.
patent: 5146308 (1992-09-01), Chance et al.
patent: 5290732 (1994-03-01), Kumar et al.
patent: 5399898 (1995-03-01), Rostoker
patent: 5656863 (1997-08-01), Yasunaga et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5773359 (1998-06-01), Mitchell et al.
patent: 5900498 (1999-05-01), Winter et al.
patent: 5900672 (1999-05-01), Chan et al.
patent: 5903058 (1999-05-01), Akram
patent: 6028362 (2000-02-01), Omura
patent: 6136707 (2000-10-01), Cohen
patent: 6144096 (2000-11-01), Lopatin
patent: 61566
Howell Wayne J.
Mendelson Ronald L.
Motsiff William T.
International Business Machines - Corporation
McGinn & Gibb PLLC
Parekh Nitin
Sabo, Esq. William D.
LandOfFree
Copper pad structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Copper pad structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Copper pad structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3285329