Copper interconnect with improved barrier layer

Details Copper interconnect with improved barrier layer Copper interconnect with improved barrier layer

2002-02-22

2004-04-27

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S761000, C257S763000, C438S648000, C438S656000, C438S683000, C438S685000, C438S687000

Reexamination Certificate

active

06727592

ABSTRACT:

TECHNICAL FIELD
The present invention relates to copper (Cu) and/or Cu alloy metallization in semiconductor devices, and to a method for manufacturing semiconductor devices with reliable, low resistance Cu or Cu alloy interconnects exhibiting improved electromigration resistance and increased via chain yield. The present invention is particularly applicable to high speed integrated circuits having submicron design features and high conductivity interconnect structures.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing reliable low RxC (resistance x capacitance) interconnect patterns with higher electromigration resistance.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization have become more prevalent as device geometry's shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening through the interlayer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interlayer dielectric is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the interlayer dielectric and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the RxC delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.12 micron and below, the rejection rate due to integrated circuit speed delays significantly reduces production throughput and increases manufacturing costs. Moreover, as line widths decrease electrical conductivity and electromigration resistance become increasingly important.
In implementing Cu metallization, particularly in damascene techniques wherein an opening is formed in a dielectric layer, particularly a dielectric layer having a low dielectric constant, e.g., a dielectric constant less than about 3.9, various reliability, elecromigration and resistance issues are generated. Reliability issues stem, in part, from the difficulty in depositing a conformal barrier, such as tantalum nitride (TaN), by physical vapor deposition (PVD) techniques which are limited by the line of sight deposition. Chemical vapor deposition (CVD) of a barrier layer would provide better conformal coverage, particularly in geometries less than 1,000 Å. However, although CVD provides superior step coverage of the barrier metal layer, a disadvantageous interaction occurs with the seedlayer which deposited by PVD. Such an adverse interaction results in degradation of the interface between the CVD barrier layer and PVD seedlayer giving rise to a high contact resistance and poor feature filling adversely impacting the reliability of the contact or via. This problem has been found difficult to resolve without sacrificing electromigration resistance and via chain yield.
Accordingly, there exist a need for reliable, low resistance Cu and Cu alloy interconnects exhibiting improved electromigration resistance and increased via chain yield, and for enabling methodology.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a semiconductor device having reliable, low resistance Cu or Cu alloy interconnects with improved electromigration resistance and increased via chain yields.
Another advantage of the present invention is the method of manufacturing a semiconductor device having reliable, low resistance Cu or Cu alloy interconnects with improved electromigration resistance and increased via chain yield.
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a semiconductor device comprising: an opening formed in a dielectric layer; a barrier layer lining the opening, the barrier layer comprising a bottom portion and side portions; a layer of tantalum (Ta), deposited by physical vapor deposition and having a thickness less than 30 Å, on the bottom portion of the barrier layer; a seedlayer on the Ta layer and over the side portions of the barrier layer; and copper (Cu) or a Cu alloy filling the opening.
Embodiments of the present invention comprise depositing an alpha (&agr;)-Ta layer by PVD at a thickness of about 5 Å to about 30 Å, e.g. at about 8 Å to about 24 Å, on the bottom portion of the barrier layer, and depositing a layer of &agr;-Ta on the side portions of the barrier layer, at a thickness less than about 10 Å, e.g., less than about 3 Å. Embodiments of the present invention further include depositing discontinuous regions of clusters of Ta atoms by PVD on the side portions of the barrier layer. Embodiments of the present invention further include forming a dual damascene opening in a dielectric layer having a relatively low dielectric constant, such as a dielectric constant (k) less than about 3.9.
Another aspect of the present invention is a method of manufacturing a semiconductor device, the method comprising: forming an opening in a dielectric layer; depositing a barrier layer by chemical vapor deposition or atomic layer deposition lining the opening, the barrier layer comprising a bottom portion and side portions; depositing a layer of tantalum (Ta) by physical vapor deposition, at a thickness less than 30 Å, on the

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