Cleaning compositions for solid surfaces – auxiliary compositions – Cleaning compositions or processes of preparing – For cleaning a specific substrate or removing a specific...
Reexamination Certificate
2003-10-14
2004-10-12
Webb, Gregory (Department: 1751)
Cleaning compositions for solid surfaces, auxiliary compositions
Cleaning compositions or processes of preparing
For cleaning a specific substrate or removing a specific...
C438S692000, C438S693000, C510S375000
Reexamination Certificate
active
06803353
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an improved composition of slurries, a process for the chemical mechanical polishing or planarization of semiconductor wafers and to semiconductor wafers made according the foregoing process.
2. Description of the Prior Art
During integrated circuit manufacture, semiconductor wafers used in semiconductor fabrication typically undergo numerous processing steps, including deposition, patterning, and etching steps. Details of these manufacturing steps for semiconductor wafers are reported by Tonshoff et al., “Abrasive Machining of Silicon”, published in the
Annals of the International Institution for Production Engineering Research
, (Volume 39/2/1990), pp. 621-635. In each manufacturing step, it is often necessary or desirable to modify or refine an exposed surface of the wafer in order to prepare the wafer for subsequent fabrication or manufacturing steps. In conventional semiconductor device fabrication schemes, a silicon wafer is subjected to numerous processing steps that deposit uniform layers of two or more discrete materials which together form a single layer of what will become a multi-layer structure. In this process, it is common to apply a uniform layer of a first material to the wafer itself or to an existing layer of an intermediate constructed by any of the means commonly employed in the art, to etch features into or through that layer, and then to fill the features with a second material. Alternatively, features of approximately uniform thickness comprising a first material may be deposited onto the wafer, or onto a previously fabricated layer of the wafer, usually through a mask, and then the regions adjacent to those features may be filled with a second material to complete the layer. Following the deposition step, the deposited material or layer on a wafer surface generally needs further processing before additional deposition or subsequent processing occurs. When completed, the outer surface is substantially globally planar and parallel to the base silicon wafer surface. A specific example of such a process is the Damascene processes.
In the Damascene process, a pattern is etched into an oxide dielectric (e.g., SiO
2
) layer. After etching, optional adhesion and or barrier layers are deposited over the oxide surface. Typical barrier layers may include tantalum, tantalum nitride, titanium nitride or titanium, or tungsten. Next, a metal (e.g., copper) is deposited over or on top of the adhesion and or barrier layers. The copper metal layer is then modified, refined or finished by removing the copper metal and regions of the adhesion and or barrier layer on the surface of the underlying dielectric. Typically, enough surface metal is removed so that the outer exposed surface of the wafer comprises both metal and an oxide dielectric material. A top view of the exposed wafer surface would reveal a planar surface with copper metal corresponding to the etched pattern and barrier layer or dielectric material adjacent to the copper metal. The copper (or other metal) and oxide dielectric material(s) located on the modified surface of the wafer inherently have different hardness values and susceptibly to controlled corrosion. The method to modify the surface of the semiconductor may be a combination of a physical and chemical process. Such a process is called chemical mechanical planarization (CMP). An abrasive CMP process used to modify a wafer produced by the Damascene process must be designed to simultaneously modify the metal (e.g., copper) and barrier layer or dielectric materials without inducing defects in the surface of either material. The abrasive process must create a planar outer exposed surface on a wafer having an exposed area of a metal and an exposed area of a dielectric material.
Chemical mechanical polishing (or planarization) (CMP) is an area in semiconductor processing undergoing rapid changes. CMP provides global (millimeter-sized dimensions) and local (micron to nanoscale-sized) planarization on the wafer surface. This planarity improves the coverage of the wafer with dielectric materials and metals (e.g., copper) and increases lithography, etching and deposition process latitudes. Various equipment companies are advancing CMP technology through improvements in the engineering aspects of CMP while chemical companies are focusing on consumables such as slurries and polishing pads. For example, conventional CMP methods for modifying or refining exposed surfaces of structured wafers uses techniques that polish a wafer surface with a slurry containing a plurality of loose abrasive particles dispersed in an aqueous medium. Typically this slurry is applied to a polishing pad and the wafer surface is rotated against the pad in order to remove the desired material from the wafer surface. Generally, the slurry may also contain chemical agents that react with the wafer surface to enhance metal removal rates.
A relatively new alternative to CMP slurry methods uses an abrasive pad to planarize a semiconductor surface and thereby eliminate the need for the foregoing slurries containing polishing particles. This alternative CMP process is reported in International Publication No. WO 97/11484, published Mar. 27, 1997. The abrasive pad has a textured abrasive surface which includes abrasive particles dispersed in a binder. During polishing, the abrasive pad is contacted with a semiconductor wafer surface, often in the presence of a working slurry containing no additional abrasive particles. The aqueous slurry is applied to the surface of the wafer to chemically modify or enhance the removal of a material from the surface of the wafer under the action of the abrasive article.
Working slurries useful in the process described above, either in conjunction with the aforementioned slurries or the abrasive pad, are typically aqueous solutions of a variety of additives including metal complexing agents, oxidizing agents, passivating agents, surfactants, wetting agents, buffers, viscosity modifiers or combinations of these additives. Additives may also include agents which are reactive with the second material, e.g., metal or metal alloy conductors on the wafer surface such as oxidizing, reducing, passivating, or complexing agents. Examples of such working slurries may be found, for example, in U.S. patent application Ser. No. 09/091,932 filed Jun. 24, 1998.
Variables that may affect wafer CMP processing include the selection of the contact pressure between the wafer surface and abrasive article, composition of the polishing pad, use of a sub-polishing pad, geometry of the grooves in the polishing pad, type of slurry medium, relative speed and relative motion between the wafer surface and the abrasive article, and the flow rate of the slurry medium. These variables are interdependent, and are selected based upon the individual metal surface being polished.
CMP processes for modifying the deposited metal layer until the barrier layer or oxide dielectric material is exposed on the wafer outer surface leaves little margin for error because of the sub-micron dimensions of the metal features found on the wafer surface. The removal rate of the deposited metal should be relatively fast to minimize the need for additional expensive CMP tools, and the metal must be completely removed from the areas that were not etched. The metal remaining in the etched areas must be limited to discrete areas while being continuous within those areas or zones to ensure proper conductivity. Thus, the CMP process must be uniform, controlled, and reproducible on a sub-micron to nano-scale dimension.
In the CMP processes mentioned above, dishing performance, scratches or defects and removal rate of the metal are measurements of CMP performance. These performance measurements may depend on the use of the foregoing working slurries and mechanical polishing processes. Dishing is a measure of how much metal, such as copper, is removed from bond pads or wire traces below the plane of the intermediate wafer surface as defined by
Carroll Glenn
Martyak Nicholas
Atofina Chemicals, Inc.
Rudman Gilbert W.
Webb Gregory
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