Copper atomic layer chemical vapor desposition

Details Copper atomic layer chemical vapor desposition Copper atomic layer chemical vapor desposition

2001-01-19

2002-10-15

Kunemund, Robert (Department: 1765)

Single-crystal, oriented-crystal, and epitaxy growth processes;

Forming from vapor or gaseous state

With decomposition of a precursor

C117S104000, C117S102000, C117S926000

Reexamination Certificate

active

06464779

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains to systems and methods for atomic layer chemical vapor deposition. More specifically, the invention pertains to methods for copper atomic layer chemical vapor deposition, particularly to deposit a seed layer prior to the electrochemical Cu fill operation in integrated circuit fabrication. It also pertains to apparatus modules for performing such deposition.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) manufacturers have traditionally used aluminum and aluminum alloys, among other metals, as the conductive metal for integrated circuits. While copper has a greater conductivity than aluminum, it has not been used because of certain challenges it presents, including the fact that it readily diffuses into silicon oxide and degrades insulating electrical properties even at very low concentrations. Recently, however, IC manufacturers have been turning to copper because of its high conductivity and electromigration resistance, among other desirable properties. Most notable among the IC metalization processes that use copper is Damascene processing.
Damascene processing is a method for forming metal lines on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter-metal dielectric). A barrier layer that blocks diffusion of copper atoms is formed over the dielectric layer topology. Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching.
In a typical copper IC process, the formation of the desired conductive wires on the chip generally begins with a seed layer, usually deposited by physical vapor deposition (PVD). The seed layer provides a conformal, conductive layer on which a thicker layer of copper is electrofilled in order to fill in the features (e.g., trenches and vias) of the semiconductor wafer. PVD has traditionally been used to form the seed layer, but does not always provide totally conformal step coverage, particularly with respect to surface features with high aspect ratios (greater than about 5:1), where aspect ratio refers to the ratio of the feature height to the feature width. Coverage that is not conformal means coverage that is uneven, i.e., thicker in some places than others, and that may include actual gaps where the metal is discontinuous, all of which are highly undesirable in IC manufacturing. Modem integrated circuit manufacturing has moved toward features with these high-aspect ratios, particularly in advanced integrated circuits where copper is used at the conductive metal, e.g., Damascene processing. For instance, a typical via may have a diameter of 0.07 &mgr;m (the width of 266 copper atoms) but have a depth of 0.4 &mgr;m, which is an aspect ratio of 5.7:1.
Chemical vapor deposition (CVD) is another process by which the seed layer can be deposited. However, poor nucleation of the copper at the barrier layer is a common problem with CVD, as is agglomeration, the latter being caused by the relatively high temperatures [>150° C.] required by CVD techniques of the current art. Both of these problems can result in non- non-conformal deposition. Also, the high substrate temperature consumes a significant fraction of the thermal budget allowed for IC manufacture. Another problem with these CVD processes is that their carbon-containing or fluorine-containing precursor compounds can cause interface contamination, thus causing poor adhesion of the copper CVD seed layer to the underlying barrier layer. This can lead to reliability problems where subsequent stress-inducing steps such as chemical mechanical polishing (CMP) are carried out.
SUMMARY OF THE INVENTION
The present invention provides systems and methods for atomic layer chemical vapor deposition (ALCVD). More specifically, the invention pertains to methods for atomic layer vapor deposition of copper, particularly to form seed layers for integrated circuit fabrication, as well as apparatus modules for performing such deposition. Copper ALCVD provides a method by which highly conformal copper layers of a single atom thickness can be applied to the substrate. Copper ALCVD thus effectively engineers the copper seed layer on an atomic level.
One aspect of the invention provides for a method for atomic layer depositing of a metal, including exposing a substrate surface to a metal precursor in order to deposit an atomic layer of the precursor, exposing the atomic layer of the precursor to an oxidizing agent, thus leaving behind an atomic layer of oxidized metal, and exposing the oxidized metal to a reducing agent, thus reducing the oxidized metal to metal and leaving an atomic layer of the metal. The metal to be deposited can be copper. The method can be repeated to form more than one atomic layer. The method can be used to deposit part or all of a seed layer in an integrated circuit manufacturing process, for example, Damascene processing.
Another aspect of the invention provides for a method for atomic layer depositing of a metal, including exposing a substrate surface to a metal precursor in order to deposit an atomic layer of the precursor, and exposing the atomic layer of the precursor leaving to an oxidizing agent, thus leaving behind an atomic layer of the metal. The metal to be deposited can be copper. The method can be repeated to form more than one atomic layer. The method can be used to deposit part or all of a seed layer in an integrated circuit manufacturing process, for example, Damascene processing.
Another aspect of the invention provides for an apparatus module for performing atomic layer chemical vapor deposition, the module including a source of organo-metal precursor to metal, a source of oxidizing agent capable of converting the precursor to metal oxide, a source of reducing agent capable of reducing the metal oxide back to elemental copper and a substrate support heated to a temperature at which a monolayer of precursor adheres to the substrate. The apparatus can also include a semiconductor wafer. The copper can be metal, and the apparatus can be used to form part or all of a seed layer for integrated circuit manufacturing.
Another aspect of the invention provides for an apparatus module for performing atomic layer chemical vapor deposition, the module including a source of organo-metal precursor to metal, a source of oxidizing agent capable of converting the precursor to metal, and a substrate support heated to a temperature at which a monolayer of precursor adheres to the substrate. The apparatus can also include a semiconductor wafer. The copper can be metal, and the apparatus can be used to form part or all of a seed layer for integrated circuit manufacturing.
These methods and apparatus are particularly useful in conformally coating features (e.g., trenches, vias and lines) having small dimensions (e.g., at most about 0.26 &mgr;m) and/or high aspect ratios (e.g. at least about 5:1). These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.


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Kaupo Kukli, Mikko Ritala, and Markku Les

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