Coplanar twin-well integrated circuit structure

Details Coplanar twin-well integrated circuit structure Coplanar twin-well integrated circuit structure

1992-03-31

1994-04-05

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257369, 257371, 257374, 257797, 437 34, 437 63, 437979, H01L 2702

Patent

active

053007972

ABSTRACT:
A structure and method is provided for fabricating an integrated circuit having an N-type well and a P-type well, with the upper surfaces of the N-type well and the P-type well coplanar. An insulating layer is formed over the integrated circuit. A first masking layer is formed over the insulating layer to define locations of a first well to be formed. An impurity of a first conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a first region. The first masking layer is removed, and a second masking layer is formed over the insulating layer to define locations of a second well to be formed. An impurity of a second conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a second region. The second masking layer is then removed. The integrated circuit is thermally heated to form the first and second wells in the substrate. If desired, sets of alignment keys may be formed in a semiconductor wafer by first forming a layer of insulating material over a semiconductor wafer, followed by forming a layer of masking material to define the locations of the sets of alignment keys and anisotropically etching into the semiconductor wafer to form the sets of alignment keys.

REFERENCES:
patent: 4947114 (1990-08-01), Schindlbeck
patent: 4985746 (1991-01-01), Asahina
patent: 5045495 (1991-09-01), Teague et al.
No Author, "Dicing Alignment Targets for Use With Pattern Recognition System", Research Disclosure, No. 340, Aug., 1992, Kenneth Mason Publications Ltd., England, Abstract No. 34015.

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