Coplanar packaging techniques for multichip circuits

Details Coplanar packaging techniques for multichip circuits Coplanar packaging techniques for multichip circuits

1988-06-17

1991-07-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437974, 26427217, 156155, H01L 2156

Patent

active

050325434

ABSTRACT:
A method for assembling and interconnecting large, high-density circuits from separately fabricated components, where conventional preassembly device testing, and conventional production techniques, can be employed in an uncomplicated process. A plurality of semiconductor chips are applied connection-side down to a temporary soluble substrate and then encapsulated. The temporary soluble substrate is then dissolved, exposing the connection side of the chips, to which electrical connections can then be made.

REFERENCES:
patent: 3158927 (1964-12-01), Saunders
patent: 3258898 (1966-07-01), Garibotti
patent: 3621565 (1971-11-01), Sandstrom
patent: 3846198 (1974-11-01), Wen et al.
patent: 3959045 (1976-05-01), Antypas
patent: 4059708 (1977-11-01), Heiss, Jr. et al.
patent: 4168998 (1979-09-01), Hasagawa et al.
patent: 4255208 (1981-03-01), Deutscher et al.
patent: 4530152 (1985-07-01), Roche et al.
patent: 4635356 (1987-01-01), Ohuchi et al.
patent: 4709468 (1987-12-01), Wilson
patent: 4711859 (1987-12-01), Argentini
patent: 4774194 (1988-09-01), Hokuyou
Johnson et al, "Silicon Hybrid Wafer-Scale Package Technology", 1986 IEEE Journal of Solid State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 845-850.
McDonald et al, "Multilevel Interconnections in Wafer-Scale Integration", J. Vac. Sci. Technol., vol. 4, No. 6, pp. 3127-3137, Nov./Dec. 1986.

Affiliated with

Also associated with

Rating

Coplanar packaging techniques for multichip circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Coplanar packaging techniques for multichip circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Coplanar packaging techniques for multichip circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-131581