Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Subsequent separation into plural bodies
Reexamination Certificate
2005-08-09
2005-08-09
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Subsequent separation into plural bodies
C438S459000
Reexamination Certificate
active
06927147
ABSTRACT:
A method of bonding lattice-mismatched semiconductors is provided. The method includes forming a Ge-based virtual substrate and depositing on the virtual substrate a CMP layer that forms a planarized virtual substrate. Also, the method includes bonding a Si substrate to the planarized virtual substrate and performing layer exfoliation on selective layers of the planarized virtual substrate producing a damaged layer of Ge. Furthermore, the method includes removing the damaged layer of Ge.
REFERENCES:
patent: 5374564 (1994-12-01), Bruel
patent: 5462883 (1995-10-01), Dennard et al.
patent: 5877070 (1999-03-01), Goesele et al.
patent: 5882987 (1999-03-01), Srikrishnan
patent: 6059895 (2000-05-01), Chu et al.
patent: 6107653 (2000-08-01), Fitzgerald
patent: 6150239 (2000-11-01), Goesele et al.
patent: 6475072 (2002-11-01), Canaperi et al.
patent: 6573126 (2003-06-01), Cheng et al.
patent: 6723622 (2004-04-01), Murthy et al.
patent: 6746902 (2004-06-01), Maa et al.
patent: 2002/0190269 (2002-12-01), Atwater et al.
patent: 2003/0013305 (2003-01-01), Sugii et al.
patent: 2004/0087119 (2004-05-01), Maa et al.
patent: 2004/0115916 (2004-06-01), Lochtefeld et al.
patent: 2004/0214434 (2004-10-01), Atwater et al.
patent: 2005/0026432 (2005-02-01), Atwater et al.
patent: 101 00 194 (2001-07-01), None
patent: 2 777 116 (1999-10-01), None
patent: WO 02/13342 (2002-02-01), None
patent: WO 02/15244 (2002-02-01), None
patent: WO 02/33746 (2002-04-01), None
A, J. Alberton-Harvey, SOI : Materials to Systems, 1966 IEEE, IEDM 96-3, pp 111-118.
“Silicon on Insulator Material Technology”; M. Bruel; Electronics Letters; Jul. 6, 1995; vol. 31, No. 14; pp. 12011202.
“Ge layer transfer to Si for photovoltaic applications”; Zahler et al., Thomas J. Watson Laboratory of Applied Physics, California Institute of Technology; pp.: 558-562.
“Transfer of 3 in GaAs film on silicon substrate by proton implantation process”; Jalaguier et al., Electronics Letters; Feb. 19, 1998; vol. 34, No. 4; pp.: 408-409.
“Electron Mobility Enhancement in Strained-Si n-MOSFETs Fabricated on SiGe-on Insulator (SGOI) Substrates”; Cheng et al., IEEE Electron Device Letters; vol. 22, No. 7, Jul. 2001; pp.: 321-323.
“Preparation of Novel SiGe-Free Strained Si on Insulator Substrates”; Langdo et al., IEEE International SOI Conference; 2002; pp.: 211-212.
“Cleaning and Polishing As Key Steps For Smart-Cut SOI Process”; Moriceau et al., IEEE International SOI Conference, Oct. 1996; pp. 152-153.
“Relaxed Silicon-Germanium on Insulator Substrate By La;yer Transfer”; Cheng et al., Journal of Electronic Materials; vol. 30, No. 12; 2001 ; pp.: L37-L39.
Fitzgerald Eugene A.
Pitera Arthuer J.
Chaudhuri Olik
Gauthier & Connors LLP
Keshavan Belur
Massachusetts Institute of Technology
LandOfFree
Coplanar integration of lattice-mismatched semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Coplanar integration of lattice-mismatched semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Coplanar integration of lattice-mismatched semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3482857