Coordinating speculative and committed state register source dat

Details Coordinating speculative and committed state register source dat Coordinating speculative and committed state register source dat

1994-01-04

1995-09-19

Eng, David Y.

Boots, shoes, and leggings

395775, 395800, 3642624, 3649462, 36493152, G06F 924, G06F 928, G06F 938

Patent

active

054524261

ABSTRACT:
A mechanism for coordinating source data in a processor, wherein a decode circuit issues instructions comprising at least one immediate valid flag and at least one logical register source. The immediate valid flag indicates whether an immediate operand for the instruction is available on an immediate data bus, and the logical register source specifies a physical register or a committed state register. A speculative result data value and a speculative source valid flag are read from the physical register, and a committed result data value is read from the committed state register. The speculative result data value and the speculative source valid flag or the committed result data value and the committed source valid flag provide a source data value and a source data valid flag for scheduling an execution of the instruction.

REFERENCES:
patent: 4903196 (1990-02-01), Pomerene et al.
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patent: 5303356 (1994-04-01), Vassiliadis et al.
G. Sohi, "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers", 1990 IEEE, pp. 349-359.
J. Smith, "Dynamic Instruction Scheduling and the Astronautics ZS-1", 1989 IEEE, pp. 21-34.
V. Popescu, et al., "The Metaflow Architecture", IEEE Micro, 1991, pp. 10-13, and 63-73.

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