Convolutional interleaver, convolutional deinterleaver,...

Details Convolutional interleaver, convolutional deinterleaver,... Convolutional interleaver, convolutional deinterleaver,...

1999-04-27

2002-06-25

Vo, Don N. (Department: 2631)

Pulse or digital communications

Systems using alternating or pulsating current

Plural channels for transmission of a single pulse train

C375S265000

Reexamination Certificate

active

06411654

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a convolutional interleaver, a convolutional deinterleaver, a convolutional interleaving method, and a convolutional deinterleaving method, which are required for digital transmission of satellite broadcasting, ground wave broadcasting, CATV broadcasting, etc, and for reading/writing of a storage unit such as a hard disk.
BACKGROUND OF THE INVENTION
A convolutional deinterleaving method is effective as a countermeasure against burst errors.
Burst errors will be briefly described taking satellite broadcasting as an example. A broadcast wave from a broadcasting station on earth is transmitted to a satellite and relayed at the satellite to a satellite broadcast receiver provided in home.
The wave transmitted from the broadcasting station through the satellite to home is subjected to interference by thunder, rain or the like in the transmission path and while the wave is subjected to such interference, errors occur in data. These errors are called “burst errors”.
In digital transmission, information for error correction is added to the original data in advance and, therefore, it is possible to correct errors so long as the errors are within a predetermined range of bits in each segment. However, since burst errors occur continuously over the range, it is impossible to correct burst errors.
So, as a countermeasure against burst errors, data to be transmitted are temporally dispersed in advance. To be specific, by temporally dispersing the data at the transmitting end, even when burst errors occur in the process of transmission, the burst errors are dispersed when recovering the temporal, positions of the dispersed data at the receiving end, whereby the burst errors can be limited within a correctable range of bit number in each data unit.
In this way, a method of temporally dispersing data to be transmitted is “convolutional interleaving”, and a method of restoring the temporal positions of the dispersed data at the receiving end is “convolutional deinterleaving”.
There has been proposed a convolutional interleaver used for the above-mentioned purpose by, for example, Japanese Published Patent Application No. Hei. 7-170201.
FIG. 13 is a block diagram illustrating a convolutional interleaver disclosed in the above-mentioned prior art. With reference to FIG. 1-3, input data which is serially input to the interleaver through an input terminal 1000 is read into a serial-parallel conversion shift register 3000 according to a high-speed clock input through a clock input terminal 2000, wherein the serial data is converted to N stages of parallel signals.
Then, the serial-to-parallel conversion shift register 3000 outputs the N stages of parallel signals together with the clock signal which has been subjected to 1/N frequency division by an N-stage frequency divider 4000. The N stages of parallel signals are respectively input to shift registers 5001, 5002, 5003, . . . , 500 (N−1) which give delays to input data thereof, wherein those parallel signals are given delay times in proportion to the stage numbers of the respective shift registers, M, 2M, 3M, . . . , (N−1) M. Then, the N stages of parallel signals which have been delayed by the shift registers 5001, 5002, 5003, . . . , 500 (N−1) are input to a parallel-to-serial conversion shift register 6006 to be converted to a serial signal. The serial signal is output from an output terminal 7000 as data obtained by interleaving the data at the input terminal 1000.
FIG. 14 is a block diagram illustrating a convolutional deinterleaver for deinterleaving the data interleaved by the convolutional interleaver shown in FIG. 13. With reference to FIG. 14, input data applied to an input terminal 11000 is read into a serial-to-parallel conversion shift resister 13000 according to a high-speed clock input through a clock input terminal 12000, wherein the input data is converted to N stages of parallel signal.
Then, the serial-to-parallel conversion shift register 11,000 outputs the N stages of parallel signals together with the clock signal which has been subjected to 1/N frequency division by an N-stage frequency divider 14000. The N stages of parallel signals are respectively input to shift registers 900 (N−1), . . . , 9003, 9002, 9001 which give delays to input data, wherein these parallel signals are given delay times in proportion to the stage numbers of the respective shift registers, (N−1) M, . . . , 3M, 2M, M. Then, the N stages of parallel signals respectively delayed by the shift registers 900 (N−1), . . . , 9003, 9002, 9001 are input to a parallel-to-serial conversion shift register 16000 to be converted to a serial signal. The serial signal is output from an output terminal 17000 as data obtained by deinterleaving the data at the input terminal 11000.
As described above, the convolutional interleaver shown in FIG. 13 or the convolutional deinterleaver shown in FIG. 14 requires multiple stages of shift registers, resulting in an increase in the circuit scale.
Meanwhile, as a prior art which can solve the above-described problem, a convolutional interleaver using a RAM has been proposed.
The structure of the convolutional interleaver is shown in FIG. 15. With reference to FIG. 15, the convolutional interleaver comprises a single port RAM 13, an input data control means 9, a select signal generating means 10, a RAM control means 11, an address generating means 3, a writing means 12, a reading means 14, and an output signal selector 15. The single port RAM 13 outputs data to the reacting means 14. The input data control means 9 outputs input of the convolutional interleaver to the input data writing means 12 and the output signal selector 15. The select signal generating means 10 outputs a control signal to the lower address selector 7 and the RAM control means 11. The RAM control means 11 outputs a control signal to the RAM 13 and the output signal selector 15. The address generating means 3 outputs an address to the writing means 12 and the reading means 14. The writing means 12 outputs an address and data to the RAM 13. The reading means 14 outputs an address and data to the RAM 13. The output signal selector 15 generates an output signal of the convolutional interleaver.
The address generating means 3 comprises an upper address generating means 4, a lower address generating means 5, and an output timing adjusting means 8. The upper address generating means 4 outputs an upper address for each channel to the output timing adjusting means 8 and the reading means 14. The lower address generating means 5 outputs a lower address for each channel to the output timing adjusting means 8 and the reading means 14.
The lower address generating means 5 comprises a counter unit 6 and a lower address selector 7. The counter unit 6 outputs a lower address For each channel to the lower address selector 7. The counter unit 6 comprises counters 60~6C corresponding to channels ch0~chC, respectively. The lower address selector 7 outputs a lower address to the output timing adjusting means 8.
Both of the select signal generating means 10 and the address generating means 3 shown in FIG. 15 serve as an input side selector in the operation principle which is later described using FIG. 16. On the other hand, both of the output signal selector 15 and the address generating means 3 serve as an output side selector in the operation principle.
Hereinafter, the operation principle of the convolutional interleaver shown in FIG. 15 will be described with reference to FIG. 16.
In FIG. 16, reference numeral 102 denotes a single port RAM which synchronizes with a clock of frequency of f, and numerals 100 and 101 denote selectors disposed at the input side and the output side of the single port RAM 102, respectively. The single port RAM 102 has multiple stages of storage areas corresponding to the respective channels and each having a bit width b, and the number of the storage areas is equal to “depth (m)×number of channels (N)” wherein m is the number of data in bit width units

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