Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1999-09-01
2001-10-02
Grant, William (Department: 2121)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S121000, C701S023000
Reexamination Certificate
active
06298274
ABSTRACT:
CROSS-REFERENCE TO RELATED
This application claims the priority benefit of Japanese Patent Application No. 10-329112, filed Nov. 19, 1998, the entire subject matter of which is incorporated herein of reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a conveyance system in a semiconductor manufacturing process and a method for processing semiconductor wafers therein, more particularly, to a method for controlling the conveyance system to shorten a TAT (Turn Around Time) during the semiconductor manufacturing process.
2. Description of the Related Art
In the related art, a semiconductor manufacturing system comprises a wafer storage for temporary storing semiconductor wafers, an automatic conveyer for conveying the semiconductor wafers, a conveyer controller for controlling the automatic conveyer, a process unit for cleaning, drying, and etching the semiconductor wafers, and a computer for administrating and controlling the semiconductor manufacturing system. The semiconductor wafers are conveyed from the wafer storage to the process unit, or from the process unit to the another process unit in response to specific instructions form the computer.
For example, in the case that the semiconductor wafers are conveyed from the process unit A to the process unit B, the computer receives a signal from the process unit A, indicating that a process of the semiconductor wafers has been completed in the process unit A, and then the process unit B which can perform the next process is searched by the computer, and simultaneously, the computer judges whether or not the process unit B is located in the same area of the process unit A or not. In the event that the process unit B is not located in the same area as the process unit A, the computer instructs the conveyer controller to let the semiconductor wafers be conveyed to the wafer storage. In the case that the process units A and B are located in the same area, the computer judges whether or not the semiconductor wafers can be conveyed to the process unit B. If not, the computer instructs the conveyer controller to let the semiconductor wafers be conveyed to the wafer storage. If yes, the computer instructs the conveyer controller to let the semiconductor wafers be conveyed to the process unit B.
However, in the semiconductor manufacturing system mentioned above, since the signal indicating the completion of the process is sent to the computer from the process unit after the process is actually completed, the semiconductor wafers being processed can not be conveyed just after completion of the process. As mentioned above, since the automatic conveyer is moved to the process unit in response to the instruction from the computer, it will take a few minutes to reach the process unit. That is, the semiconductor wafers being processed have to wait at the process unit for a few minutes until the automatic conveyer reaches there. Therefore, the waiting time of the semiconductor wafers being processed which is the period from the time of the process completion until the time of the arrival of the automatic conveyer, causes a delay for the production TAT. Furthermore, this delay causes another delay in a later process. Further, during the conveyance of the semiconductor wafers from a wafer process unit to the assemble process unit, the semiconductor wafers could be left out of the search list of the computer by the delay even if the semiconductor wafers to be processed in the assemble process should be listed for the computer search. Furthermore, the assemble process unit is halted for awaiting the arrival of the semiconductor wafers where the semiconductor wafers under the conveyance is the only object to be processed.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a novel and efficient conveyance system for processing semiconductor wafers.
It is a more specific object of the present invention to provide a conveyance system for processing semiconductor wafers with a warning signal which indicating that a process will be completed soon.
It is an another object of the present invention to provide a conveyance system for processing semiconductor wafers having a signal for confirming whether or not there are semiconductor wafers to be processed in the wafer storage.
It is a still another object of the present invention to provide a conveyance system for processing semiconductor wafers having a watchdog timer for comparing a estimated time of process completion with a time of actual completion of the process.
It is a further object of the present invention to provide a conveyance system for processing semiconductor wafers having a delay timer for delaying an operation of the automatic conveyer to start to move to the process unit.
An advantage of my invention is that it provides the total process time can be reduced, and an operating efficiency can be improved.
To achieve the advantage of the invention, the present invention provides a process unit processing a semiconductor wafer, a conveyer conveying the semiconductor wafer, a conveyer controller controlling the conveyer, and a computer controlling the conveyer and the conveyer controller, wherein the process unit sends a warning signal to the computer, indicating time of the process completion in the process unit before the process is completed, and wherein the conveyer is moved to the process unit by the conveyer controller in response to the warning signal.
To achieve the advantage of the invention, the present invention further provides the conveyer being arranged to arrive at the process unit at the substantially same time as a completion of the process to the semiconductor wafer.
To achieve the advantage of the invention, the present invention further provides a watchdog timer for being set for a estimated time of process completion in the process unit, and wherein the watchdog timer is activated after the computer receives the warning signal.
To achieve the advantage of the invention, the present invention further provides a wafer storage for storing a wafer to be processed in the process unit, wherein the computer checks whether there is a wafer in the wafer storage, wherein the automatic conveyer moves to the wafer storage to pick up the wafer, then move to the process unit if there is the wafer in the wafer storage, and wherein the automatic conveyer moves directly to the process unit without stopping by the wafer storage if there is no wafer.
To achieve the advantage of the invention, the present invention further provides a delay timer for being set for a period of the time equal to the difference between a time that a conveyer reaches the process unit via the wafer storage and a time that a conveyer reaches the process directly, and whereby an operation of the conveyer can be delayed for the period of time equal to the difference when there is no wafers in the wafer storage.
Further to achieve the advantage of the invention, the present invention provides the step of processing the semiconductor wafer in a process unit, sending a warning signal to a computer from the process unit before the process is completed, the warning signal indicating the process is completed in few minutes, sending an instruction to a conveyer controller from the computer, the instruction including information where a automatic conveyer moves to and where the semiconductor wafer is conveyed to, and conveying the semiconductor wafer by the automatic conveyer in response to the instruction.
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Cabrera Zoila
Grant William
Mimura Junichi
OKI Electric Industry Co., Ltd.
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