Boots – shoes – and leggings
Patent
1994-10-28
1996-06-04
Mai, Tan V.
Boots, shoes, and leggings
364748, G06F 700, G06F 738
Patent
active
055239617
ABSTRACT:
Exponent conversion logic implements floating point exponent conversion of single/double precision to an extended format (IEEE 754 standard), such as in the floating point unit of an x86 processor. The SP (single precision)/DP (double precision) to EP (extended precision exponent conversion technique avoids using an adder (with the attendant propagation delay). For SP exponents (8 bit), the exponent conversion logic implements conversion to EP format (15 bits) as follows (FIG. 3a): (a) transferring the 7 LSB (least significant bits) of the SP exponent (41) as the corresponding 7 LSBs of the EP format (42), (b) inverting the MSB (most significant bit) of the SP exponent and using it as the 7 next most significant bits of the EP format, and (c) transferring the MSB of the SP exponent of the MSB of the EP. The operation for converting DP exponents (11 bits) to EP format is analogous. The same exponent conversion techniques are used to reconvert extended format exponents to single and double precision exponents.
REFERENCES:
patent: 3389379 (1968-06-01), Erickson et al.
patent: 4831575 (1989-05-01), Kuroda
patent: 4949291 (1990-08-01), Saini
patent: 5268855 (1993-12-01), Mason et al.
Cyrix Corporation
Mai Tan V.
Maxin John L.
Viger Andrew S.
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