Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1997-12-29
2003-07-29
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06601079
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor microprocessors, and, more particularly, to the way that “ordinary” floating point data representations are distinguished from “extraordinary” floating point data representations.
2. Description of the Related Art
Floating point data can typically have different representations. Commonly, a user conforming, for example, to the standard Institute of Electrical and Electronic Engineers (IEEE) formats will provide data to a microprocessor in single precision real, double precision real or extended precision real formats. Because of the difficulty in performing mixed format arithmetic operations (e.g., multiplication of a single precision real number by a double precision real number), many microprocessors convert floating point data to a predetermined standard format before beginning any operation. All the arithmetic operations are then performed, using the data converted to the predetermined standard format. After all arithmetic operations have been completed, the result is usually converted back to any desired user format.
A floating point number A includes a significand (or mantissa or fraction) S
a
and an exponent E
a
. The value of the floating point number A is given by the equation A=S
a
r
E
a
where r is the radix (or base) of the number system. The significand is usually normalized by requiring that the most significant digit (or the leftmost digit) be nonzero. Use of the binary radix (i.e., r=2) gives maximum accuracy, but may require more frequent normalization than use of higher radices.
Floating point numbers are capable of representing a wide range of values, from very large values to very small values, while maintaining the same precision throughout. Although a variety of data types are possible, floating point numbers usually assume one of the standard IEEE formats shown in FIG.
1
. For example,
FIG. 1
shows a 32-bit single precision real binary number, according to the IEEE 754 Standard (
IEEE Standard for Floating
-
Point Arithmetic
, IEEE Std 754-1985, reaffirmed 1990), having a sign S bit
10
, a biased exponent E(
8
) portion
11
, having 8 bits, and a significand F(
23
) (or mantissa or fraction) portion
12
, having 23 bits. The normalized value of such a 32-bit single precision real binary number, according to the IEEE 754 Standard, is given by the equation A
32sp
=(−1)
S
1.F(
23
)2
E(8)−127
where the “binary point” (similar to the decimal point in base-
10
) is immediately to the right of the most significant bit. Similarly,
FIG. 1
shows a 64-bit double precision real binary number, according to the IEEE 754 Standard, having a sign S bit
13
, a biased exponent E(
11
) portion
14
, having 11 bits, and a significand F(
52
) (or mantissa or fraction) portion
15
, having 52 bits. The normalized value of such a 64-bit double precision real binary number, according to the IEEE 754 Standard, is given by the equation A
64dp
=(−1)
s
1.F(
52
)2
E(11)−1023
where the binary point is again immediately to the right of the most significant bit.
FIG. 1
shows an 80-bit extended double precision real binary number, according to the IEEE 754 Standard, having a sign S bit
19
, a biased exponent E(
15
) portion
17
, having 15 bits, and a remaining portion, having 64 bits, including a significand F(
63
) (or mantissa or fraction) portion
18
, having 63 bits and a single J-bit). The normalized value of such an 80-bit extended precision real binary number, according to the IEEE 754 Standard, is given by the equation A
80ep
=(−1)
S
(i)
J
1.F(
63
)2
E(15)−16383
where i is the square root of (−1) and the binary point is still immediately to the right of the most significant bit.
FIG. 1
also shows an exemplary 86-bit internal binary representation useful in a microprocessor, having a sign S bit, a biased exponent E(
17
) portion
20
, having 17 bits, and a remaining portion, having 68 bits, including a significand F(
63
) (or mantissa or fraction) portion
21
, having 63 bits, a single I-bit, a single J-bit, a single Guard bit, a single Round bit and a single Sticky bit. By using such an internal representation that is larger than any of the IEEE Standard formats that a microprocessor can accommodate, overflow and rounding errors that normally occur during arithmetic operations may be virtually eliminated, for example.
The B-bit biased exponent E
bias
(B) ranges from 0 to 2
B
−1 in the IEEE Standard format binary floating point representations because the relative sizes of the biased exponents E
bias
(B) of different floating point numbers are then simpler to determine. The effective value of the exponent of the binary radix (r=2) is determined by subtracting a bias value 2
(B−1)
−1 from the B-bit biased exponent value E
bias
(B). The range of effective values of the exponent of the binary radix (r=2) is from −(2
(B−1)
−1) to 2
(B−1)
, corresponding to the B-bit biased exponent E
bias
(B) range of from 0 to 2
B
−1, respectively.
The IEEE Standard format binary floating point representations having B-bit biased exponents E
bias
(B) ranging from 1 to 2
B
−2 are “ordinary” or “nonexceptional” binary floating point representations. The IEEE Standard format binary floating point representations having B-bit biased exponents E
bias
(B) of 0 or 2
B
−1 are “extraordinary” or “exceptional” binary floating point representations. A B-bit biased exponent value E
bias
(B)=0 in the IEEE Standard format binary floating point representations serves as a flag or token for the number 0 (if the significand value is also 0) and for denormalized or subnormalized numbers (if the significand value is not also 0). A B-bit biased exponent value E
bias
(B)=2
B
−1 in the IEEE Standard format binary floating point representations serves as a flag or token for infinity (if the significand value is 0) and for “Not a Number” (NaN) indicators (if the significand value is not 0).
The conversion between different floating point representation formats is a low-level, performance-critical operation. As such, the conversion between different floating point representation formats is typically performed by various floating point hardware circuits. In some cases, however, the floating point hardware circuits cannot perform the conversion between different floating point representation formats because of the coincidence of the conversion with other system events, such as a cache line split on a memory operand, for example. In these cases, a floating point software handler performs the conversion between different floating point representation formats. Doing this conversion involves two relatively independent operations: (1) rounding the significand, and (2) converting the exponent.
As described above, the exponent field is made up of B bits, giving 2
B
possible binary exponent representations that each belong to one of two classes of representations: “ordinary” binary floating point representations, corresponding to an actual exponent for a binary-encoded floating point number, and “extraordinary” binary floating point representations, corresponding to entities such as zero, infinity and “Not a Number” (NaN) that are not otherwise readily encoded by binary floating point representations. When converting a floating point quantity between two different representations, the function to be applied to the exponent field depends on the respective class of the binary floating point representation. It would be desirable to distinguish, and to make distinctions between, the two classes of binary floating point representations, to discriminate quickly and reliably between the “ordinary” and the “extraordinary” binary floating point representations and to detect, and to filter out, the “extraordinary” binary floating point representations, as needed.
The cases where the floating point hardware circuits cannot perform the conversion
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Mai Tan V.
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