Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-11-30
2004-06-01
Nguyen, Chau (Department: 2663)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S466000, C370S351000, C370S230000, C370S474000
Reexamination Certificate
active
06744772
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer networks. More particularly, the present invention converts asynchronous packets into isochronous packets for transmission through a multi-dimensional switched fabric network.
2. Description of the Prior Art
Data transmitted through a computer network includes asynchronous or “best-effort” data and isochronous or “time-constrained” data. Asynchronous data is injected into the network at arbitrary intervals and forwarded to a destination node within an unconstrained (best-effort) time interval. An example of asynchronous data is transaction data transmitted between an end user and a service provider (e.g., a web site). Isochronous data, in contrast, is typically injected into the network at a periodic interval and forwarded to a destination node within a predetermined time-constrained interval. An example of isochronous data is a video stream which must be transmitted to an end user at a guaranteed periodic interval to facilitate uninterrupted viewing.
Details of a prior art method for transmitting best-effort and time-constrained data through a multi-dimensional switched fabric network are disclosed by Jennifer Rexford, et al. in “A Router Architecture for Real-Time Communication in Multicomputer Networks”,
IEEE Transactions on Computers
, Vol. 47, No. 10, October 1998, which is incorporated herein by reference. Rexford suggests to implement a switched node using a data structure (a queue or virtual cache) for best-effort data and a separate data structure (another queue or virtual cache) for time-constrained data. Rexford also suggests to prioritize virtual lanes so that on-time time-constrained data is transmitted through the switch ahead of any pending best-effort data. However, the additional hardware support needed to handle best-effort data using a separate data structure increases the complexity and cost of the switch. In addition, giving absolute priority to time-constrained data can degrade the performance of the network with respect to best-effort data, which may be undesirable. Further, it is not possible to control the variance in transmitting best-effort data if it is always transmitted subordinate to time-constrained data. Best-effort data may also subject the network to deadlock, a condition where a packet cannot advance toward the destination node because the buffers (or other resources) in the path cannot be allocated to transmit the packet.
There is, therefore, a need to improve performance of a multi-dimensional switched fabric network for both isochronous (time-constrained) as well as asynchronous (best-effort) data. In particular, there is a need to simplify the circuitry within each switched node, to mitigate blocking of asynchronous data by isochronous data, to control transmission variance, and to mitigate deadlock.
SUMMARY OF THE INVENTION
The present invention may be regarded as a switched node for use in a multi-dimensional switched fabric network. The switched node comprises adapter circuitry connected to receive asynchronous and isochronous packets from an external entity. Each asynchronous packet comprises destination node routing information and data, and each isochronous packet comprises a path ID corresponding to a reserved path through the network, an arrival time parameter identifying a target arrival time of the isochronous packet into the switched node, and data. An asynchronous-to-isochronous converter converts the asynchronous packets into isochronous packets comprising the data from the asynchronous packets. A plurality of bi-directional ports receive isochronous packets from other switched nodes and transmit isochronous packets to other switched nodes. A data buffer stores the isochronous packets received from the bi-directional ports, the isochronous packets received from the adapter circuitry, and the isochronous packets comprising the asynchronous data. Routing circuitry selects at least one of the bi-directional ports to output the stored isochronous packets, and assigns a departure time parameter to each of the stored isochronous packets. A scheduler, responsive to the target arrival times and the departure times, schedules the transmission of the stored isochronous packets through at least one of the bi-directional ports
In one embodiment, the asynchronous-to-isochronous converter comprises a microprocessor for reserving a path through the network for transmitting the isochronous packets comprising the data from the asynchronous packets. In one embodiment, the path is reserved by routing a request packet through the switched fabric between the source and destination nodes, wherein resources are reserved along the path of the request packet. In another embodiment, the microprocessor schedules the transmission of the isochronous packets comprising the data from the asynchronous packets. In yet another embodiment, the switched node further comprises an isochronous-to-asynchronous converter for converting isochronous packets comprising asynchronous data into asynchronous packets for transmission by the adapter circuitry to the external entity.
The present invention may also be regarded as a multi-dimensional switched fabric network comprising a plurality of interconnected switched nodes. A select number of the switched nodes comprise adapter circuitry connected to receive asynchronous and isochronous packets from an external entity. Each asynchronous packet comprises destination node routing information and data. Each isochronous packet comprises a path ID corresponding to a reserved path through the network, an arrival time parameter identifying a target arrival time of the isochronous packet into the switched node, and data. An asynchrbnous-to-isochronous converter within the switched nodes converts the asynchronous packets into isochronous packets comprising the data from the asynchronous packets. The switched nodes comprise a plurality of bi-directional ports for receiving isochronous packets from other switched nodes and for transmitting isochronous packets to other switched nodes. A data buffer within the switched nodes stores the isochronous packets received from the bi-directional ports, the isochronous packets received from the adapter circuitry, and the isochronous packets comprising the asynchronous data. Routing circuitry within the switched nodes selects at least one of the bi-directional ports to output the stored isochronous packets, and stores a departure time parameter for each of the stored isochronous packets. A scheduler within the switched nodes, responsive to the target arrival times and the departure times, schedules the transmission of the stored isochronous packets through at least one of the bi-directional ports.
The present invention may also be regarded as a multi-dimensional switched fabric network comprising a plurality of interconnected switched nodes and an input for receiving asynchronous and isochronous packets from host initiators. Each asynchronous packet comprises destination node routing information and data. Each isochronous packet comprises a path ID corresponding to a reserved path through the network, an arrival time parameter identifying a target arrival time of the isochronous packet into each switched node, and data. A central microprocessor converts the received asynchronous packets into isochronous packets comprising the data from the asynchronous packets. Each switched node comprises a plurality of bi-directional ports for transmitting the received isochronous packets and the isochronous packets comprising the data from the asynchronous packets through the network. A data buffer stores the received isochronous packets and the isochronous packets comprising the data from the asynchronous packets. Routing circuitry selects at least one of the bi-directional ports to output the stored isochronous packets. The routing circuitry also stores a departure time parameter for each of the stored isochronous packets. A scheduler schedules, responsive to the target arrival times and the departure times,
Eneboe Michael K.
Hospodor Andrew D.
Juntima Nittaya
Nguyen Chau
Shara, Esq. Milad G.
Sheerin, Esq. Howard H.
Western Digital Ventures, Inc.
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