Converter systems having reduced-jitter, selectively-skewed...

Details Converter systems having reduced-jitter, selectively-skewed... Converter systems having reduced-jitter, selectively-skewed...

2007-03-20

2008-09-30

Jeanglaude, Jean B (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S156000

Reexamination Certificate

active

07429944

ABSTRACT:
Converter systems are provided that use particular combinations of fixed and variable clock skewers to generate interleaved clock signals for the systems. These combinations have been found effective in accurately generating selectively-skewed clocks while simultaneously restricting the jitter that generally accompanies the skewing process.

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patent: 6525577 (2003-02-01), Lee
patent: 6542017 (2003-04-01), Manganaro
patent: 7053804 (2006-05-01), Nairn
Looney, Mark, “Advanced Digital Post-Processing Techniques Enhance Performance in Time-Interleaved ADC Systems”, Analog Dialogue, vol. 37, Aug. 2003, 5 pages.

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