Converter for interconnecting an asynchronous telecommunication

Details Converter for interconnecting an asynchronous telecommunication Converter for interconnecting an asynchronous telecommunication

1990-12-13

1993-08-24

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 601, H04Q 1104, H04L 1266

Patent

active

052395448

ABSTRACT:
The converter comprises a memory (SRAM) having first and second ports, a first port management circuit (SPM) connected to the first port, to an incoming synchronous multiplex line (ME) and to an outgoing synchronous multiples line (MS), and a second port management circuit (APM) connected to the second port, to an incoming asynchronous link (LE) via an FIFO type packet memory (M) and to an outgoing asynchronous link (LS). An external command (MF) applied to the port management circuits selects the converter operating mode; in a first mode (M32) each time slot of a frame of a synchronous multiplexed signal is assigned to one communication channel and in a second mode (M1) all the time slots of a synchronous frame are assigned to one channel.

REFERENCES:
patent: 4541076 (1985-09-01), Bowers et al.
patent: 4612636 (1986-09-01), Grover et al.
patent: 4761781 (1988-09-01), Calvaniac et al.
patent: 4805167 (1989-02-01), Leslie et al.
patent: 4808008 (1989-02-01), Guerillot
patent: 4893303 (1990-01-01), Chao et al.
patent: 5008878 (1991-04-01), Ahmadi et al.

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