Converter circuit for converting 1-redundant representation...

Details Converter circuit for converting 1-redundant representation... Converter circuit for converting 1-redundant representation...

2007-03-22

2008-12-02

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S493000

Reexamination Certificate

active

07461107

ABSTRACT:
A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.

REFERENCES:
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patent: 5050120 (1991-09-01), Houk
patent: 5181186 (1993-01-01), Al-Ofi
patent: 5289398 (1994-02-01), Miyoshi et al.
patent: 5986587 (1999-11-01), Fukuda
patent: 2002/0174157 (2002-11-01), Bhushan et al.

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