Converter circuit arrangement with minimal snubber

Details Converter circuit arrangement with minimal snubber Converter circuit arrangement with minimal snubber

1996-06-26

1998-03-24

Wong, Peter S.

Electric power conversion systems

Current conversion

Including automatic or integral protection means

363135, H02H 7122

Patent

active

057319677

ABSTRACT:
A converter circuit arrangement in which the gate turn-off thyristors are driven hard, i.e., the GTO is driven with a gate current configured in such a way that the turn-off gain IS/IGpeak is distinctly less than 3 so as to result in an anode voltage rise of at least 1 kV/.mu.s. The snubber circuit of such driven thyristors may be designed to include only a small number of elements. The voltage rise limiter includes at least one capacitor connected in parallel with one of the reverse-connected parallel diodes. The current rise limiter includes a parallel circuit having an inductor and a current limiting diode.

REFERENCES:
patent: 4881159 (1989-11-01), Holtz et al.
patent: 5448467 (1995-09-01), Ferreira
McMurray, William; "Efficient Snubbers For Voltage-Source GTO Inverters"; IEEE Transactions On Power Electronics, vol. PE-2, No. 3, Jul. 1987, pp. 264-272.
Japanese Abstract of JP 1-81669 (A); E-787, Jul. 13, 1989; vol. 13; No. 307, English Translation.
Article entitled: "An Overview of Low-Loss Snubber Technology For Transistor Converters" by A. Ferraro, IEEE 1982, pp. 466-477.

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