Multiplex communications – Communication over free space – Combining or distributing information via code word channels...
Reexamination Certificate
2000-09-21
2004-04-06
Pham, Chi (Department: 2667)
Multiplex communications
Communication over free space
Combining or distributing information via code word channels...
C370S441000
Reexamination Certificate
active
06717933
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a converter and a method for converting an input data packet stream of consecutive data packets into an output data symbol stream of data symbols. The respective data packets of the input data packet stream each include user data in the form of consecutive data symbols, wherein each of the data packets are provided by a plurality of N user channels having respectively different predetermined transmission rates. In the output data symbol stream respectively corresponding data symbols from the individual input data packets are sequentially arranged.
The invention particularly relates to an encoder of a CDMA transmitter, in which such a converter is used to provide the respective data symbols consecutively to a CDMA modulator in which the respective data symbols are convoluted with respective codes (e.g. Walsh-codes) having a length e.g. dependent on the spreading factor provided for each channel in the output data symbol stream. Although the converter can be used independently as to whether or not the data packets from the respective user channels arrive asynchronously or synchronously at the encoder, after the converter a synchronous processing (synchronous with respect to the symbol length of a symbol at the basic transmission rate in the air) of the data is required and preferably different data rates should be supported.
BACKGROUND OF THE INVENTION
Since the invention generally relates to a transmitter of a CDMA-system and in particular to the encoding, interleaving and modulating units of an encoder unit of the CDMA-system, more specifically to the problem of how a plurality of user channels each having a different transmission rate and sending user data as data packets can be combined into a data symbol stream to be processed and CDMA modulated for all channels at the same time, hereinafter, first a general overview of a base station transmitter of a CDMA-system is described with reference to FIG.
1
.
In
FIG. 1
, ATM-IFC is an ATM interface board, ENC is the channel encoder, interleaver, QPSK selector and time alignment unit; BBTX is the CDMA modulation, spreading and combining unit, BBIF is an interface board, BBRX is the CDMA demodulator and despreader for dedicated channels, DEC is the Viterbi decoder for dedicated channels, BBPA is the random access receiver (including a decoding unit), and DC-FILT is the power supply. Asynchronously arriving data packets are input to the encoder ENC at {circumflex over (
2
)}. The TRX-DIG unit is a digital pulse shaping filter & digital/analog conversion unit.
FIG. 2
shows the encoder ENC with more details. On a plurality of channels ch-
0
, ch-
1
. . . ch-N−1 a plurality of N users input data packets DP
0
, DP
1
. . . DP
N−1
of variable length (due to the variable transmission rates TR
0
, TR
1
, . . . TR
N−1
) which arrive at the FPGA at {circumflex over (
2
)} (Field Programmable Gate Array). Essentially, in the encoder ENC in
FIG. 2
, data for user channels and data for common control channels undergo a convolutional encoding at {circumflex over (
6
)}, {circumflex over (
7
)} and essentially serial bit streams are input to the FPGA {circumflex over (
3
)}, which performs the interleaving, time alignment etc. Data is output to the CDMA modulator (indicated with “BBTX-board” in
FIG. 2
) from the FPGA {circumflex over (
5
)}. As explained below, the data of common control channels are input to the digital signal processor DSP {circumflex over (
1
)}.
As is indicated in
FIG. 2
, the input data of the user channels ch-
0
, ch-
1
, . . . ch-N−1 arrive from the ATM-IFC unit (an asynchronous transfer mode interface unit) in data packets DP
0
, DP
1
, DP
2
. . . DP
N−1
asynchronously at the first FPGA {circumflex over (
2
)}. That is, the transmission of data packets of the respective N user channels ch-
0
, ch-
1
. . . ch-N−1 takes place using an asynchronous transfer method (ATM). As is schematically indicated in
FIG. 2
, within each frame defined by a frame synchronization clock supplied by a main controller, one single packet of each user channel must be processed, i.e. as is shown in
FIG. 2
, the user data packets DP
0
, DP
1
, DP
2
, . . . DP
N−1
arriving asynchronously must be processed in a standard frame period of for example T=10 ms.
In
FIG. 2
, the DSP at {circumflex over (
1
)} is a digital signal processor which receives configuration data and data packets for the common control channels, configures FGPAs and processes common control channels to the FPGA {circumflex over (
6
)}. The ATM packets for dedicated physical channels (DPCH) (=user traffic data) are input to the FPGA {circumflex over (
2
)} as explained above. The FPGA {circumflex over (
3
)} is essentially a write means for the interleaver and converter (and the time alignment). {circumflex over (
4
)} is a memory means for the interleaver and converter (and the time alignment). {circumflex over (
5
)} is a read means for the interleaver and converter (and time alignment) for providing an output symbol stream to the CDMA modulator. {circumflex over (
6
)} is a convolutional encoder for common control channels. {circumflex over (
7
)} is a convolutional encoder for dedicated physical channels. {circumflex over (
8
)} is a unit for performing a frame buffering for dedicated physical channels. In the unit {circumflex over (
8
)} some synchronisation of the incoming asynchronous input data bit stream is performed if more than one packet arrives for a single channel within the predetermined frame period. This synchronisation ensures that after the unit {circumflex over (
8
)} only one respective single packet of all channels is processed within the frame period.
DESCRIPTION OF THE RELATED ART
On the basis of the above explanations with respect to FIG.
1
and
FIG. 2
,
FIG. 3-1
shows a principle block diagram of an encoder ENC to illustrate the underlying problem of the invention. In principle, the blocks indicated in
FIG. 2
are also present inherently in FIG.
2
.
FIG. 3-2
shows the processing of data packets from the input to the output of the encoder board in several consecutive frames m, m+1, m+2.
As shown in
FIG. 3-1
, there are a plurality of users US
0
, US
1
. . . US
N−1
transmitting data packets DP on respective user channels ch-
0
, ch-
1
. . . ch-N−1. As shown with the time line at 10 ms, 20 ms, 30 ms on the left side in
FIG. 3-1
it should be understood that actually the packets DP arrive asynchronously at the encoder ENC. Within each frame interval of e.g. 10 ms one data packet of each channel arrives asynchronously.
As mentioned above, if more than one data packet arrives for a channel within the frame interval then the unit {circumflex over (
8
)} synchronizes i.e. processes these packets in such a way that only one packet per frame interval and channel is input to a parallel/serial converter P/S and thus to the convolutional encoder CC (unit {circumflex over (
7
)} in FIG.
2
). Hereinafter, it is assumed that always one packet arrives asynchronously per channel and frame interval, either because indeed only one packet arrives or because several packets have been processed in the correct manner by the unit {circumflex over (
8
)}. The parallel/serial converter P/S shown in
FIG. 3-1
is preferably arranged between the units {circumflex over (
8
)} and {circumflex over (
7
)} in
FIG. 2
, i.e. before the convolutional encoder CC as shown in
FIG. 3-1
. However, completely independent of the location and structure of the parallel/serial converter P/S and the structure of the units {circumflex over (
2
)}, {circumflex over (
3
)}, the important aspect is that the convolutional encoder CC (unit {circumflex over (
7
)} in
FIG. 2
) receives a serial data bit stream SDBS comprising a single packet of each channel per frame interval. For example, if the units {circumflex over (
2
)}, {circumflex over (
8
)}, are already provided with said serial data bit stream SDBS, then the parallel/serial converter is not nec
Huaman-Bollo Gian
Sönning Raimund
Ly Anh-Vu
Pham Chi
Telefonaktiebolaget LM Ericsson (publ)
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