Pulse or digital communications – Pulse width modulation
Reexamination Certificate
1999-11-30
2003-07-15
Chin, Stephen (Department: 2634)
Pulse or digital communications
Pulse width modulation
C332S109000
Reexamination Certificate
active
06594308
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electronics, and, more particularly, to a driving technique through an output power bridge for an electromagnetic R-L actuator.
BACKGROUND OF THE INVENTION
An example of a conversion system for an N-bit digital value in a pulse width modulation (PWM) signal is disclosed in European Patent Application No. 96,830,295 filed on May 22, 1996, which is assigned to the assignee of the present invention. The disclosed conversion system sets N equal to eight.
Numeric values from sampling (digitizing) a suitably optimized driving waveform may be read from one or more nonvolatile memory buffers, and multiplied by a modulating variable whose magnitude is determined by the control system. The magnitude is dependent upon the force, torque or speed required by the electromagnetic actuator. The resulting numeric value is written in a register. A certain pre-established number (N) of most significant bits resulting from the multiplication are thereafter used as the driving numeric value.
Such a conversion system is shown in
FIG. 1
, and is based upon comparing the input BYTE (N=8) with the status of an 8-bit timer functioning in a continuous up/down mode. The input BYTE represents the sample value to be converted. In
FIGS. 1 and 2
, the BYTE (N=8) input sample is synchronously loaded into the SL register to avoid a sample updating during the conversion. The comparator COMP generates a clock pulse for the latch FF
2
each time the counter CNT equals the value of the sample to be converted. The output is a PWMOUT signal having a duty cycle that varies proportionally with the input value, and symmetrically with respect to the maximum count value of the counter.
As shown in
FIG. 2
, the unit increment of the input sample value to be converted determines a double and symmetric decrement of the output duty cycle. The unit increment is highlighted in the figure. In
FIG. 2
, the transition from the value
188
to the value
189
determines the duty cycle variation, as represented by a dashed-line.
When driving an output bridge stage, the current is controlled in a pulse shift modulation (PSM) mode according to a technique that is commonly implemented in these types of power drivers. A description of which may be found in European Patent No. EP 0760552, granted Mar. 3, 1997, which is assigned to the assignee of the present invention. In the disclosed technique, two values must be converted, one for each output half bridge having a value symmetrical to 2
N
.
In these applications, a unit increment of the value forced in a half bridge corresponds to a unit decrement of the value forced in the other half bridge to maintain the above cited symmetry. This implies a double differential increment of the duty cycle.
SUMMARY OF THE INVENTION
An object of the invention is to avoid the above described duty cycle variations for unit value variations for input samples of a bridge driving system.
A pulse width modulation (PWM) driving technique for an output bridge stage controls the voltage applied to the actuator to determine the current that actually flows through it. The PWM control signal is generated by a circuit that converts an N-bit digital value into a digital signal having an amplitude compatible with the input characteristics of the output stage. The output signal has a fixed frequency and a duty cycle proportional to the input value.
The method of the present invention separately handles the four instants of comparison between the input data and the output of the up/down counter. This is while ensuring that the minimum variation of the duty cycle is substantially halved by using the half clock period of the system. This allows seven intermediate levels of duty cycle variations to be obtained between any two consecutive values of the input data having eight bits.
According to another aspect of the invention, an increment of the conversion process is achieved by increasing a certain number of bits, e.g., N to N+3, the size of the driving numeric value to be converted without increasing the number of bits of the up/down counter in which the comparison is carried out. The size of the driving numeric value commonly results from the product of a sampled value with a modulating value.
REFERENCES:
patent: 4233591 (1980-11-01), Murata et al.
patent: 4590457 (1986-05-01), Amir
patent: 6310912 (2001-10-01), Maiocchi et al.
patent: 0 892 500 (1999-01-01), None
patent: 0 897 213 (1999-02-01), None
Chrappan Soldavini Francesco
Galbiati Ezio
Papillo Lorenzo
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Chin Stephen
Jorgenson Lisa K.
Odom Curtis
STMicroelectronics S.r.l.
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