Conversion circuit with duty cycle correction for small...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control

Utility Patent

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C327S051000

Utility Patent

active

06169434

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuits. More particularly, the present invention relates to integrated circuit interfaces that facilitate high-speed clocking and data transmission.
2. Description of the Related Art
High-speed clocking is a goal in many digital systems. For example, high speed clocking is important in achieving high-speed data buses used with microprocessors, memories (e.g., DRAM, SRAM, Flash devices), and ASICs. These high-speed clocks may be small signal clocks with voltage swings of, for example, 400 mV to 600 mV. Further, the duty cycle of the clock signal may not be 50% because of imperfect clock sources, parasitics on or coupled to a clock bus, other integrated circuits in the clock path, and many other factors.
An integrated circuit receives the high-speed clock and uses it to synchronize its operation. In order to use the signal internally within a CMOS integrated circuit, it is frequently necessary to convert a small signal clock to CMOS levels, which typically range from ground to VCC (“full-rail”). In order to enhance predictability and allow greater performance margins, the clock signal should have a 50% duty cycle. A 50% duty cycle means that in a single cycle the digital high signal has the same duration as the digital low signal. In a clocking scheme where both rising and falling edges of the clock signal are used for clocking, a 50% duty cycle is critical in improving performance margins.
In view of the foregoing, it would be highly desirable to provide an apparatus and method for improved processing of small swing signals. Ideally, such a technique would include the capability to perform duty cycle correction.
SUMMARY OF THE INVENTION
A duty cycle correcting amplifier includes a first differential transistor pair with a pair of input nodes for receiving a differential input signal to be amplified. The first differential transistor pair has a first common node and a first pair of output nodes carrying differential output signals. A first current source is connected between the first common node and a first supply voltage. A second differential transistor pair has a pair of input nodes for receiving differential error input signals. The second differential transistor pair has a second common node and a second pair of output nodes coupled to the first pair of output nodes. The second differential transistor pair alters the common mode levels of each of the first pair of output nodes based on the differential error input signals to affect the duty cycle of the differential output signals. A second current source is connected between the second common node and the first supply voltage. A load circuit is connected between the first pair of output nodes and a second supply voltage. The load circuit provides a high impedance load between each node of the first pair of output nodes and a low impedance between each node of the first pair of output nodes and the second supply voltage. Capacitive circuitry is connected to each node of the first pair of output nodes. A converting amplifier has a pair of inputs for receiving the differential output signals. The converting amplifier amplifies and converts the differential output signals to a single ended signal constituting the output of the duty cycle correcting amplifier.
The circuit provides amplification for fixed sized small swing signals. In particular, amplification up to full-rail CMOS levels is achieved. The circuit is low power and has low inherent distortion and process tracking.


REFERENCES:
patent: 5696724 (1997-12-01), Koh et al.
patent: 5696726 (1997-12-01), Tsukikawa

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