Controlling which of two addresses is used by a microcode memory

Details Controlling which of two addresses is used by a microcode memory Controlling which of two addresses is used by a microcode memory

1979-11-30

1981-11-10

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 922

Patent

active

043002080

ABSTRACT:
A microcode addressing system is shown which has two modes of operation for different memory search functions. The first mode, the Slow mode in which the memory operates at a standard read rate, is the mode in which the computer central processing unit performs predetermined sequential tasks in a normal fashion. The second mode of operation is the Fast mode of operation in which the memory responds to unpredetermined, dynamically changing events in the computer system at a faster than standard cycle time in order to search for and identify a particular word in central memory.

REFERENCES:
patent: 3938100 (1976-02-01), Steiner
patent: 4079451 (1978-03-01), Woods et al.
patent: 4095278 (1978-06-01), Kihara

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