Controlling timing in asynchronous digital circuits

Details Controlling timing in asynchronous digital circuits Controlling timing in asynchronous digital circuits

2011-07-19

2011-07-19

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S392000

Reexamination Certificate

active

07982518

ABSTRACT:
A timing circuit for generating asynchronous signals is provided that uses minimal area while maximizing speed. This timing circuit can include a timing control block and disable/enable circuitry. The timing control block can include an SR latch and first and second delay blocks. The SR latch can generate first and second signals, wherein the first and second signals are asynchronous. The first delay block can generate a delayed first signal and provide that signal to a first input terminal of the SR latch. Similarly, the second delay block can generate a delayed second signal and provide that signal to a second input terminal of the SR latch. Notably, the first and second delay blocks delay positive going edges of the first and second signals differently than negative going edges of the first and second signals.

REFERENCES:
patent: 5430681 (1995-07-01), Sugawara et al.
patent: 5581507 (1996-12-01), Scherpenberg et al.
patent: 5808492 (1998-09-01), Chow
patent: 7579892 (2009-08-01), Kadanka
patent: 7656240 (2010-02-01), Wong et al.
patent: 2007/0273423 (2007-11-01), Kadanka

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