Controlling timeslot delay in a digital communication system

Details Controlling timeslot delay in a digital communication system Controlling timeslot delay in a digital communication system

2005-05-27

2010-06-22

Moe, Aung S (Department: 2474)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S394000, C370S458000

Reexamination Certificate

active

07742506

ABSTRACT:
A buffer circuit for use in a digital communication system includes a memory and a controller coupled to the memory. The memory is configurable for storing a plurality of data frames of a first data stream, each of the data frames including a plurality of timeslots corresponding to respective channels in the digital communication system. The controller is operative to store data from the first data stream into corresponding timeslots in the memory in a first order, to individually adjust delays of the respective timeslots as a function of respective delay control parameters, and to generate a second data stream by reading the timeslots stored in the memory in a second order.

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