Controlling threading dislocation densities in Ge on Si using gr

Details Controlling threading dislocation densities in Ge on Si using gr Controlling threading dislocation densities in Ge on Si using gr

1998-06-23

2000-08-22

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Having graded composition

257616, H01L 310256

Patent

active

061076538

ABSTRACT:
A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer oil the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.

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Currie et al., "Controlling Threading Dislocation in Ge on Si Using Graded SiGe Layers and Chemical-Mechanical Polishing," vol. 72 No. 14, p. 1718-1720, Feb. 1998.

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