Controlling the system time clock of an MPEG decoder

Details Controlling the system time clock of an MPEG decoder Controlling the system time clock of an MPEG decoder

2005-11-29

2005-11-29

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

C375S373000, C375S240280, C375S376000, C375S368000, C331S017000, C713S503000, C711S219000, C348S441000, C370S503000, C704S500000

Reexamination Certificate

active

06970526

ABSTRACT:
During decoding and processing of program clock reference (PCR) values in MPEG-2 transport streams, a first initial difference value is obtained by calculating a difference between a first detected PCR value and a system time clock (STC) value generated when the first PCR value is detected. Depending on the update status of the PCR values, a second initial difference value is obtained by calculating a difference between a second detected PCR value and a STC value generated when the second PCR value is detected. Thereafter, a composite difference value is obtained by further calculating a difference between the first initial difference value and the second initial difference value. Subsequently, the first and second initial difference values, and the composite difference values are calculated for a predetermined number of detected PCR values so that the decoder clock signal is generated and maintained at approximately the same frequency as an encoder clock signal.

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