Controlling power up using clock gating

Details Controlling power up using clock gating Controlling power up using clock gating

1995-11-06

1998-10-13

Harvey, Jack B.

395556, H03K 2100, G06F 1300

Patent

active

058225960

ABSTRACT:
During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.

REFERENCES:
patent: 4758945 (1988-07-01), Remedi
patent: 4893271 (1990-01-01), Davis et al.
patent: 5142684 (1992-08-01), Perry et al.
patent: 5222239 (1993-06-01), Rosch
patent: 5325074 (1994-06-01), Suenaga
patent: 5355502 (1994-10-01), Schowe et al.
patent: 5369771 (1994-11-01), Gettel
patent: 5418969 (1995-05-01), Matsuzaki et al.
patent: 5524035 (1996-06-01), Casal et al.

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