Electrical computers and digital processing systems: multicomput – Computer-to-computer data addressing
Reexamination Certificate
2007-03-06
2007-03-06
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data addressing
C709S238000, C712S015000
Reexamination Certificate
active
10838071
ABSTRACT:
A method and apparatus for providing local control of processing elements in a network of multiple context processing elements (MCPEs). A MCPE stores configuration memory contexts and maintains data of a current configuration. State information is received from at least one other MCPE. A configuration control signal is generated in response to the state information and current configuration data. A MCPE is selected in response to the configuration control signal to control the MCPE. Each MCPE in the networked array has an assigned physical and virtual identification. Data comprising control data, configuration data, an address mask, and a destination identification is transmitted to a MCPE. The transmitted address mask is applied to either a physical or a virtual identification, and to a destination identification. The masked physical or virtual identification is compared to the masked destination identification. When the masked physical or virtual identification matches the masked destination identification, a MCPE is manipulated in response to the transmitted data by selecting one of a number of configuration memory contexts to control the functioning of the MCPE.
REFERENCES:
patent: 4597041 (1986-06-01), Guyer et al.
patent: 4748585 (1988-05-01), Chiarulli et al.
patent: 4754412 (1988-06-01), Deering
patent: 4858113 (1989-08-01), Saccardi
patent: 4870302 (1989-09-01), Freeman
patent: 5020059 (1991-05-01), Gorin et al.
patent: 5233539 (1993-08-01), Agrawal et al.
patent: 5276683 (1994-01-01), Ohkubo
patent: 5301340 (1994-04-01), Cook
patent: 5317209 (1994-05-01), Garverick et al.
patent: 5336950 (1994-08-01), Popli et al.
patent: 5386413 (1995-01-01), McAuley et al.
patent: 5426378 (1995-06-01), Ong
patent: 5457408 (1995-10-01), Leung
patent: 5469003 (1995-11-01), Kean
patent: 5581199 (1996-12-01), Pierce et al.
patent: 5684980 (1997-11-01), Casselman
patent: 5712974 (1998-01-01), Gainey et al.
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5754818 (1998-05-01), Mohamed
patent: 5765209 (1998-06-01), Yetter
patent: 5778439 (1998-07-01), Trimberger et al.
patent: 5815723 (1998-09-01), Wilkinson et al.
patent: 5880598 (1999-03-01), Duong
patent: 5956518 (1999-09-01), DeHon et al.
patent: 6023564 (2000-02-01), Trimberger
patent: 6047122 (2000-04-01), Spiller
patent: 6085317 (2000-07-01), Smith
patent: 6101599 (2000-08-01), Wright et al.
patent: 6128656 (2000-10-01), Matchefts et al.
patent: 6339819 (2002-01-01), Huppenthal et al.
Valero-Garcia, et al.; “Implementation of Systolic Algorithms Using Pipelined Functional Units”; IEEE Proceedings on the International Conf. On Application Specific Array Processors; Sep. 5-7, 1990; pp. 272-283.
Razdan, et al.; “A High-Performance Microarchitecture with Hardware-Programmable Functional Units”; Micro-27 Proceedings of the 27thAnnual International Symposium on Microarchitecture; Nov. 30-Dec. 2, 1994; pp. 172-180.
Guo, et al.; “A Novel Programmable Interconnect Architecture with Decoded Ram Storage”; Proceedings of the IEEE Custom Integrated Circuits Conference; May 1-4, 1994; pp. 193-196.
Vuillemin, et al.; “Programmable Active Memories: Reconfigurable Systems Come of Age”; IEEE Transactions on VLSI Systems; 1995; pp. 1-15.
Hon, et al.; “Reinventing Computing,” Mar. 1996; MIT A1 Lab, p. 1.
Baker, “Programming Silicon”; Aug. 28, 1995, Electronic Engineering Times; p. 73.
Brown; “Smart Compilers Puncture Code Bloat”; Oct. 9, 1995; Electronic Engineering Times; pp. 38 and 42.
Snyder; “A Taxonomy of Synchronous Parallel Machines”; Proceedings of the 1988 International Conference on Parallel Processing; Aug. 15-19, 1998; pp. 281-285.
Gray, et al.; “Configurable Hardware: A New Paradigm for Computation”; 1989; Massachusetts Institute of Technology; pp. 279-296.
Carter et al.; “A User Programmable Reconfigurable Logic Array”; IEEE 1986 Custom Integrated Circuits Conference; pp. 233-235.
Johnson, et al.; “General-Purpose Systolic Arrays”; IEEE Nov. 1993; pp. 20-31.
Clark; “Pilkington preps reconfigurable video DSP”; EE Times, week of Jul. 31, 1995.
Fiske, et al.; “The Reconfigurable Arithmetic Processor”; The 15thAnnual International Symposium on Computer Architecture; May 30-Jun. 2, 1988; pp. 30-36.
Beal, et al.; Design of a Processor Element for a High Performance Massively Parallel SIMD System; Int'l Journal of High Speed Computing, vol. 7, No. 3; Sep. 1995; pp. 365-390.
Snyder; “An Inquiry into the Benefits of Multiguage Parallel Computation”; Proceedings of the 1995 International Conference on Parallel Processing; Aug. 20-23, 1995; pp. 488-492.
Wang, et al.; “An Array Architecture for Reconfigurable Datapaths: More FPGAs,” W. R. Moore & W. Luk; 1994 Abingdon EE&CS Books; pp. 35-46.
Bridges; “The GPA Machine: A Generally Partionable MSIMD Architecture”; IEEE Third Symposium on The Frontiers of Massively Parallel Computation, Feb. 1990; pp. 196-203.
Morton, et al.; “The Dynamically Reconfigurable CAP Array Chip I”; IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986; pp. 820-826.
Alexander, et al.; “A Reconfigurable Approach to a Systolic Sorting Architecture”; IEEE Feb. 1989; pp. 1178-1182.
Blazek, et al.; “Design of a Reconfigurable Parallel RISC-Machine”; North-Holland Microprocessing and Microprogramming, 1987; pp. 39-46.
Masera, et al.; “A Microprogrammable Parallel Architecture for DSP”; Proceedings of the International Conference on Circuits and Systems, Jun. 1991; pp. 824-827.
Xilinx Advance Product Information: “XC6200 Field Programmable Gate Arrays”; Jan. 9, 1997 (Version 1.8); pp. 1-53.
Sowa, et al.; “Parallel Execution on the Function-Partitioned Processor with Multiple Instruction Stream”; Systems and Computers in Japan, vol. 22, No. 4, 1991; pp. 22-27.
Wang, et al.; “Distributed Instruction Set Computer”; Proceedings of the 1988 International Conference on Parallel Processing; Aug. 15-19, 1988; pp. 426-429.
Mirsky, Ethan A., “Coarse-Grain Reconfigurable Computing”; Thesis submitted at the Massachusetts Institute of Technology, Jun. 1996.
Eslick Ian
French Robert
Mirsky Ethan
Broadcom Corporation
Kim Kenneth S.
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