Excavating
Patent
1992-09-23
1998-09-22
Lane, Jack A.
Excavating
365201, 36523005, 711211, G11C 2900
Patent
active
058125590
ABSTRACT:
A control method and apparatus for the examination of multiport RAM(s) connected between a CPU on a CPU side and a hardware circuit on a hardware circuit side. The method and apparatus are for use in a device comprising a single RAM or more. For instance, the device may have a first RAM and a second RAM having ports on CPU and a hardware circuit side of the RAMs. Each one port on the CPU side is connected to a CPU. The method and apparatus examine the ports on the hardware circuit as well as the CPU side ports. The method may comprise steps of reading data stored in the first RAM from a port on the hardware circuit of the first RAM and writing the data in the second RAM from the port on the hardware circuit side of the second RAM using a RAM examination controller. The data read from the one port of the first RAM on the CPU side of the RAMs is compared with the data from the other port of the second RAM on the CPU side of the RAMs. The operation of ports of the first RAM and the second RAM on the hardware circuit side of the RAMs is examined.
Hiyama Shinzi
Ikuta Koji
Nakaide Hiroshi
Saito Fumihiko
Fujitsu Limited
Lane Jack A.
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