Controlling data transfer between two microprocessors by receivi

Details Controlling data transfer between two microprocessors by receivi Controlling data transfer between two microprocessors by receivi

1992-12-08

1996-06-04

Lee, Thomas C.

Boots, shoes, and leggings

39520013, 3642291, 3642707, 3649402, 364DIG1, G06F 104

Patent

active

055242375

ABSTRACT:
A microprocessor communication system couples two microprocessors over a bus comprising a bidirectional data line, a bidirectional sync line and a pair of clock lines. A toggled clock signal serves as a control signal. Each microprocessor outputs data to the data and sync lines and monitors its incoming clock line. When a toggled clock signal is sensed, the receiving microprocessor, when its priorities permit, takes control of the bus and stops outputting data to the data and sync lines. It then detects the incoming data and when incoming data reception is completed, the microprocessor outputs new information to the data and sync lines and toggles its output clock line to signal to the other microprocessor that control of the bus has been relinquished. With the system, the microprocessors operate without the constraints of predetermined time intervals in which to output data or to receive data.

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