Controller for initiating insertion of wait states on a signal b

Details Controller for initiating insertion of wait states on a signal b Controller for initiating insertion of wait states on a signal b

1995-08-30

1997-04-22

Heckler, Thomas

395878, G06F 104

Patent

active

056236484

ABSTRACT:
A controller for initiating an insertion of one or more wait states on a signal bus includes registers, AND logic circuits, a counter and a OR logic circuit. One register is for connecting to a signal bus and receiving therefrom a clock signal and in response thereto receiving and latching an address strobe signal to provide a latched address strobe signal. One AND logic circuit is for receiving the latched address strobe signal, connecting to the signal bus and receiving therefrom an address write signal and a chip select signal and logically. ANDing the latched address strobe signal, the address write signal and the chip select signal to provide a first ANDed signal. Another register is for receiving a second clock signal and in response thereto receiving and latching the first ANDed signal to provide a first latched ANDed signal. Another AND logic circuit is for receiving and logically ANDing the first latched ANDed signal and a decoded address signal to provide a second ANDed signal. The counter is for receiving the second ANDed signal and the second lock signal and in response thereto providing a multiple-bit count signal. The OR logic circuit is for receiving and logically ORing the first latched ANDed signal and the multiple-bit count signal to provide a wait state control signal for initiating an insertion of one or more wait states on the signal bus.

REFERENCES:
patent: 5201036 (1993-04-01), Yoshimatsu
patent: 5396599 (1995-03-01), Cobbs et al.
patent: 5581745 (1996-12-01), Muraoka et al.

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