Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2001-04-17
2003-01-07
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S035000, C327S561000
Reexamination Certificate
active
06504409
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electronic circuits for generating periodic output signals. The present invention relates more specifically to an electronic circuit that allows linear voltage control of the width of a periodically repeating digital pulse, and therefore provides continuously variable duty cycle ratio control of an output clock signal that is synchronous with an input clock signal.
2. Description of the Related Art
One of the most useful electronic circuits is one that generates a digital (a periodic on-off) signal for controlling the operation of one or more digital or digitally controllable devices. It is most useful when the ratio of the on-time during each cycle to the off-time of the cycle, that is, the duty cycle ratio, can be easily varied and controlled. In some embodiments of the basic controller circuit, the linear variance of an analog device, that might for example provide an adjustable voltage, current, or resistance in the circuit, is translated into a linear variation in the duty cycle ratio of the output digital signal.
A number of different types of digitally based duty cycle controllers are known in the art, and may include a modulo-N counter-timer in cascade with a modulo-M counter-timer, where N+M is held constant and defines the output clock frequency, while the period of an input reference clock determines the resolution. Another method employs a shift register having a series of fixed delay interval stages with interposed user selectable taps. According to this method, the output delay or duty cycle ratio is established in discrete steps that depend on the tap selected and on the fixed time delay contributed by each of the internal delay stages.
Normally, the propagation delay of a simple digital gate (or flip-flop) defines the duty cycle adjustment granularity, that is, the shortest incremental delay step achievable. U.S. Pat. No. 5,682,114 issued to Ohta, however, teaches another time delay control technique wherein the differences between the charging time constants of MOSFET gate capacitances provide a relatively shorter single stage delay. Furthermore, each single stage delay can be directly varied by digitally controlling how many MOSFET gate capacitances are connected in parallel at each delay node. Multiple stages can be cascaded for longer delays.
A similar technique for producing short selectable delay intervals is taught in U.S. Pat. No. 5,933,039 issued to Hui et al., wherein the delay at each node is fine-tuned during manufacture. Each nodal capacitance is held constant while the effective nodal charging current is adjusted to properly calibrate each of the individual time delay steps. To achieve longer delay periods, these stages may be concatenated as needed under user programming control.
The basic output element of most analog time delay designs constitutes a detector whose output changes state when a time varying input voltage crosses its input switching threshold. A current source, or a voltage source driving a resistor serving as a voltage-to-current converter, connected to a capacitor generates a time varying voltage that may serve as the input to the detector. Initially, the voltage across the capacitor may be set to a known value to force the detector output into a given state s
0
. At a particular time, known as the trigger point, current is allowed to flow into the capacitor causing its the voltage to rise until a threshold voltage is reached whereupon the detector output switches to state s
1
. The time elapsed between these two events is determined by four analog circuit parameters: capacitance, initial capacitor voltage, charging current and detector input switching threshold voltage. If a reset mechanism for the capacitor voltage is provided, this circuit becomes formally equivalent to a retriggerable monostable multivibrator, similar to the well known 555 timer. In principle any one or more of these analog timing parameters can be varied to change the length of the time delay.
The simplest pulse width controller consists of a dual input AND gate, whose inputs exhibit substantially constant and equal switching threshold points, configured with one input being driven directly by the external clock while the other is connected to an RC low pass filter circuit driven by the same external clock; in this case, the voltage developed across the capacitor follows an exponentially decaying curve. With the inputs connected in this manner, the output can assume a logic high value only when the voltages of both the master clock as well as the output of the RC network exceed the gate's input switching threshold, so the duty cycle exhibited at the output of the gate will be determined by the delay due to the low pass filtering action of the RC network. Should the values of either passive element be variable in response to a suitable control signal, then adjustable time delay could be achieved.
Another common technique for analog time delay control is based on the use of an adjustable current source to produce a linear ramping capacitor voltage, with the other three timing parameters identified earlier being held constant. For example, an enhancement recommended for the 555 timer specifies the use of a simple transistor constant current source to linearize the capacitor charging current. Unfortunately, this is only useful for pulse widths down to tenths of a microsecond. In U.S. Pat. No. 4,843,255 issued to Steubing, a design for a fast (500 MHz), step-wise adjustable monostable multivibrator is disclosed wherein the charging current for the timing capacitor is the controlled parameter. By using a voltage controlled current sink to discharge a timing capacitor that has been preset to a known voltage, an accurate time delay is produced at the output of a suitable detector means. The current sink node is the collector terminal of a single common base transistor configured so that a voltage may be impressed across its emitter resistor by a precision DAC. The output of the DAC is connected to provide a relatively negative voltage with respect to the emitter, drawing a current out of the emitter resistor that is substantially equal to the sink current flowing into the collector. Base current compensation is also provided to improve performance.
A continuously variable monostable design, employing a ramp generator consisting of an adjustable current controlled current source and a fixed capacitor, is disclosed in U.S. Pat. No. 5,410,191 issued to Miura, where it appears as an embedded circuit within an FM demodulator. A more sophisticated compound technique to achieve precise timing over relatively long time periods is taught in U.S. Pat. No. 5,124,597 issued to Steubing et al., where the ramp type delay generator described in Steubing (255) is placed in cascade with a series of high speed timer-counter sections. The ramp delay means provides small step-wise vernier delay increments to the primary delay set by a number of cascaded counter-timer stages.
All of the methods described above are examples of open-loop pulse width and timing generators, that could in principle be used as part of a duty cycle controller. However, in every open-loop method, both accuracy and stability are dependent on the absolute values of internal analog quantities such as ramp timing capacitance and nodal charging currents. A significant level of precision can be achieved, but only at the expense of relatively complex circuitry.
On the other hand, a considerable increase in performance can be immediately realized by enclosing a basic retriggerable pulse width modulator within a high gain feedback loop that provides continual correction to the duty cycle ratio of an output clock signal, forcing it to track the value of an input control signal. Because of the fundamental difference in form between the controlling input (an analog voltage or current) and output (a stream of digital pulses), the feedback arrangement takes the form of a servo control loop. An output clock signal that
Callahan Timothy P.
Cox & Smith Incorporated
K-Tek Corporation
Luu An T.
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