Controller for disabling a data bus

Details Controller for disabling a data bus Controller for disabling a data bus

1990-12-08

1992-06-02

Mis, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307242, H03K 1756

Patent

active

051189704

ABSTRACT:
A software controlled system having a signal source connected to logic circuits via data busses. User operated circuitry permits any selected data bus to be temporarily isolated from the signal source so that maintenance and/or logic circuit replacement may be performed on the isolated data bus.

REFERENCES:
patent: 3757138 (1973-09-01), Bhatia et al.
patent: 3849726 (1974-11-01), Justice
patent: 4196360 (1980-04-01), Miller et al.
patent: 4438494 (1984-03-01), Budde et al.
patent: 4870704 (1989-09-01), Matelan et al.
"Open Line Detection On CPU Channel Bus", Bersac and Calvignac, IBM Technical Disclosure Bulletin, vol. 26, No. 4, Sep. 1983, pp. 2037-2038.
"CMOS Static Memory with a New Four-Transistor Memory Cell", Lyon and Schediwy, 1987 Stanford Conference 111-32, pp. 111-132.
"Testing's Impact On Design & Technology", 1986 IEEE International Test Conf., Sep. 8-11, 1986, paper 4.4, pp. 161-168.
"A Line-Driver And Receiver Circuit With Signal-Level Recognition", Gottlicher and Hauenstein, Elektronik V. 29, N. 17, 21 Aug. 1980, pp. 63-66.

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