Controller for bubble memories

Details Controller for bubble memories Controller for bubble memories

1978-10-30

1980-09-30

Boudreau, Leo H.

Boots, shoes, and leggings

365 1, 365200, G11C 1908

Patent

active

042259410

ABSTRACT:
This invention discloses a method for the simultaneous control and management of an arbitrary number of bubble memories, whereby the existence, locations, and defects of the blemished data positions in the bubble memory devices are managed by the invention, allowing the external device using the bubble memories to no longer be cognizant of the blemished data positions of the bubble memories. Specifically, this invention uses a shift register connected in a parallel manner to the bubble memories, a second shift register connected to the external data bus, a means for storage for the valid data positions in the bubble memory devices, and a means for gating data between the two shift registers in a serial manner, the gating means being controlled by the memory containing the valid data positions.

REFERENCES:
patent: 3792450 (1974-02-01), Bogar et al.
patent: 3896421 (1975-07-01), Flannery
patent: 3921156 (1975-11-01), Yoshimi
patent: 3990058 (1976-11-01), Archer et al.
patent: 4001673 (1977-01-01), Barrett et al.
patent: 4045779 (1977-08-01), Markle
patent: 4070651 (1978-01-01), Naden
patent: 4073012 (1978-02-01), Ohnigian et al.
patent: 4090251 (1978-05-01), Flannigan et al.
patent: 4125875 (1978-11-01), Saito
patent: 4139886 (1979-02-01), White et al.

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