Boots – shoes – and leggings
Patent
1979-04-17
1982-04-27
Zache, Raulfe B.
Boots, shoes, and leggings
371 3, 371 16, G06F 300
Patent
active
043274080
ABSTRACT:
A controller for interfacing a central processor unit (CPU) to a peripheral storage device which can be tested for proper operation independent of the peripheral storage device includes a sequencer, a buffer, a microprocessor and various error detection logic. A gate is coupled between the sequencer and the input of the peripheral storage device for enabling or disabling the transfer of data from the sequencer to the peripheral storage device and a multiplexer is coupled between the microprocessor, the output of the peripheral storage device and the sequencer for selecting inputs to the sequencer from either the microprocessor or the peripheral storage device. During a normal write operation, write signals are sent from the CPU to the sequencer through the buffer and then from the sequencer to the peripheral storage device through the gate. During a normal read operation, read signals are sent from the peripheral storage device to the sequencer through the multiplexer and then from the sequencer to the CPU through the buffer. During a test write operation, the input to the peripheral storage device is disabled and write signals that would normally be sent from the sequencer to the peripheral storage device are sent to the microprocessor and then from the microprocessor to the CPU. During a test read operation, simulated read signals are generated in the microprocessor, sent from the microprocessor to the sequencer through the multiplexer and then sent from the sequencer to the CPU through the buffer.
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Frissell John M.
Swanson Kris E.
Data General Corporation
Kriegsman Irving M.
Rappaport Irving
Wall Joel
Zache Raulfe B.
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