Controlled slew rate buffer

Details Controlled slew rate buffer Controlled slew rate buffer

1990-11-08

1992-08-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3075421, 307542, 307448, 307451, 307452, 307263, 307475, H03K 1716

Patent

active

051381940

ABSTRACT:
A controlled slew rate buffer is disclosed which comprises a driver receiving voltage along a voltage supply line and includes feedback apparatus which senses the noise level along the voltage supply line and slows the speed of the buffer when the noise level passes a given threshold. The driver comprises at least one of (1) first and second VSS voltage sources and (2) first and second VDD voltage sources.

REFERENCES:
patent: 4110704 (1978-08-01), Irwin et al.
patent: 4408137 (1983-10-01), Fox
patent: 4638187 (1987-01-01), Boler et al.
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4779013 (1988-10-01), Tanaka
patent: 4806802 (1989-02-01), Okitaka et al.
patent: 4862018 (1989-08-01), Taylor et al.
patent: 4959561 (1990-09-01), McDermott et al.
Leung, Kam, "Controlled Slew Rate Output Buffer", IEEE 1988 IEEE 1988 Custom Integrated Circuits Conference 5.5.1-5.5.4.

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