Fishing – trapping – and vermin destroying
Patent
1986-03-07
1988-04-12
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 39, 437 40, 437 59, 357 22, 357 43, H01L 2970, H01L 2980
Patent
active
047374691
ABSTRACT:
A standard JFET or MESFET with a second gate is described. The second gate underlies the channel region, but is accessible from the same surface of the semiconductor body as are the other terminals of the transistor. Electrical signals are transmitted to the second gate by a heavily doped interconnect region. Isolation techniques prevent a voltage applied to this second gate from having a significant effect on adjoining electronic devices. Also described is a process for manufacturing such transistors using only steps which are present in a typical bipolar processing sequence.
REFERENCES:
patent: 4228450 (1980-10-01), Anantha et al.
patent: 4546370 (1985-10-01), Curran
Muggli, IBM Tech. Disc. Bull., v. 24(2), pp. 997-998 (Jul., 1981).
Chaudhuri Olik
Honeywell Inc.
Udseth William T.
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