Controlled linewidth reduction during gate pattern formation usi

Details Controlled linewidth reduction during gate pattern formation usi Controlled linewidth reduction during gate pattern formation usi

1997-08-01

1999-10-12

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438725, 438734, 438952, H01L 21302

Patent

active

059654619

ABSTRACT:
A gate is formed by depositing a gate conductive layer over a substrate layer, depositing an organic spin-on bottom anti-reflective coating (BARC) over the gate conductive layer, and forming a resist mask on the BARC. Next, the resist mask is controllably etched to further reduce the critical dimensions of gate pattern formed therein, and then the gate is formed by etching the gate conductive layer using the reduced size resist mask.

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G.V. Thakar, V.M. McNeil, S.K. Madan, B.R. Riemenschneider, D.M. Rogers, J.A. McKee, R. H. Eklund and R.A. Chapman, "A Manufacturable High Performance Ouarter Micron CMOS Technolgy Using I-Line Lithography and Gate Linewidth Reduction Etch Process", IEEE 1996, p. 216-217.
Wei W. Lee, Qizhi He, Maureen Hanratty, Dary Rogers, Amitava Chatterjee, Robert Kraft and Richard A. Chapman, "Fabrication of 0.06 um Poly-Si Gate Using DUV Lithography With a Designed Si.sub.X O.sub.Y N.sub.Z Film as an Arc and Hardmask", IEEE, Jan., 1997, p. 131-132.

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