Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1999-02-04
2001-05-22
Gaffin, Jeffrey (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S321200, C029S852000, C333S206000, C174S261000, C174S262000
Reexamination Certificate
active
06236572
ABSTRACT:
BACKGROUND
The disclosures herein relate generally to printed circuit boards (PCB's) and methods for manufacturing printed circuit boards. More particularly, the disclosures herein relate to printed circuit boards for use in a computer system having at least one bus exhibiting controlled impedance characteristics.
Plug-in memory modules are commonly used in personal computers (PC's). These modules connect to the motherboard of a PC through an electrical connector that is mounted on the motherboard, allowing additional memory and memory with improved performance to be installed. RAMBUS™ Incorporated offers a line of high-performance memory modules called RAMBUS In-Line Memory Modules, also known as RIMM™ modules. The RIMM modules are based on the electrical requirements of a technology known as the Direct RAMBUS Channel. This technology is a high-speed bus operating at clock speeds of 400 MHz or more, enabling data rates of 800 bps or more. To maintain high signal integrity, the bus uses transmission line characteristics. Of these characteristics, controlled impedance is key.
The use of RAMBUS RIMM modules requires that the interface between the memory and the memory controller have a nominal impedance of 28 ohms with a maximum tolerance of +/−20%. In cases where RAMBUS memory and the memory controller are mounted on the same PCB, a PCB having a tolerance of +/−20% is acceptable. However, in the case of a RIMM module, where the memory and memory controller reside on separate PCB's, the PCB's used for the RIMM module as well as the motherboard must have an impedance of 28 ohms with a maximum tolerance of +/−2.8 ohms (+/−10%). This specification ensures that the combined tolerance of the RIMM module and the memory controller PCB is not more than +/−20%.
This impedance specification is tighter than the present capability of PCB manufacturers. The geometric variations of the dielectric thickness and trace widths at the current limits of PCB manufacturability will provide 28 ohms with a tolerance of +/−4.8 ohms (+/−20%). Empirical data shows that vendors can, with an extra degree of care, reach a tolerance of +/−3.44 ohms. Even then, testing is still required to select the PCB's that satisfy the required tolerance for RAMBUS memory. Therefore, PCB's for use with high performance memory such as RAMBUS RIMM Modules currently have to be 100% tested, at least for initial production boards. This increases the cost of the PCB's for these types of applications and results in increased yield loss. Consequently, the cost of the devices and machines in which these boards and RAMBUS memory are used is also increased.
Current bus construction techniques for 4 layer PCBs provide a one-sided dielectric and bus reference plane configuration wherein the bus signal trace has a bus reference plane and dielectric substrate on one side only. As a result, the impedance continually increases with increasing dielectric thickness. For buses having this type of construction, the relationship between the dielectric thickness d
1
and the impedance results in the impedance being difficult to maintain within a tightly controlled range without instituting expensive manufacturing and testing procedures.
Current six-layer PCBs have two pair of signal layers with a reference voltage plane between each pair of signal layers (i. e. signal-ref-signal-signal-ref-signal). As such, routing of a bus signal trace is currently provided on the outermost signal layers with a reference plane on only one side of the bus signal trace layer. As with a four-layer PCB, the use of only one reference voltage plane limits the ability to tightly control the impedance of the bus. The bus signal traces are typically not located on the inner signal layers as this would result in excessive cross-talk between the two busses.
U.S. Pat. No. 5,677,515 to Selk et al discloses a shielded printed wiring board which provides electrical and magnetic isolation for the signal layers located thereon. The printed wiring board includes a signal layer laminated between two non-conductive dielectric layers. The bottom side of the printed wiring board has a conductive layer coated thereon. Grooves are routed through the printed circuit board on both sides of each signal layer extending from the top layer partially through to the conductive layer. Conductive metallic coatings are then provided to coat the board and thereby encapsulate the signal layer in a ground envelope, separated by a controlled thickness dielectric. In an alternate embodiment, a plurality of layers are laminated one on top of the other to provide a multilayer printed wiring board. This reference does not disclose a circuit construction suitable for a memory module bus as disclosed herein. In particular, the signal layers and reference plane layers do not provide a suitable controlled impedance bus.
U.S. Pat. No. 5,278,524 to Mullen discloses a multi-layered printed circuit board for mounting and interconnecting the terminals of multi-terminal electronic components. The circuit board mounts the electronic components one side of the circuit board and provides for interconnecting the terminals of the electronic components. A transmission line arrangement is configured from layers of the circuit board for distributing a signal with fast rise and fall times to electronic components mounted on the circuit board. The transmission line arrangement includes a narrow conductive strip surrounded by four constant voltage conductors spaced from the narrow conductive strip by dielectric material. The constant voltage conductors comprise a first planar conductive layer above the narrow conductive strip and spaced therefrom by one of the dielectric layers, a second planar conductive layer below the narrow conductive strip and spaced therefrom by the other dielectric layer, and a pair of coplanar conductive strips between the two layers of dielectric material and lying parallel to and coplanar with the narrow conductive strip, one on each side of the narrow conductive strip. The invention additionally encompasses a panel board embodiment in which the transmission line arrangement, including at least two constant voltage planes surrounding the narrow conductive strip, is embedded in the multi-layered board. This reference does not disclose a suitable six-layer PCB construction providing transmission line impedance characteristics for a bus as described herein. The PCB construction disclosed in this reference positions the bus signal traces on the signal layers of the PCB. Furthermore, the technique of using vias to interconnect the constant voltage conductors surrounding each signal trace is not disclosed.
U.S. Pat. No. 5,150,088 to Virga et al discloses stripline shielding structures for stripline conductors implemented in unitized multilayer circuit structures. The stripline structures generally include a lower ground plane below the stripline conductor, one or more embedded ground planes above the stripline conductor, and conductive elements laterally spaced from the stripline conductor for electrically connecting the ground planes. Resistive layers may be included above the embedded ground plane(s) for additional shielding. This reference does not disclose a circuit construction suitable for a memory module bus as disclosed herein. In particular, the signal layers and reference plane layers do not provide a suitable controlled impedance bus.
Accordingly, a need has arisen for a PCB construction and method of manufacture in which the shortcomings of the previous techniques are overcome. More particularly, a need has arisen for a cost-effective 6-layer PCB construction and method of manufacture that can provide the impedance level and tolerance required by high-performance memory modules such as the RAMBUS RIMM modules.
SUMMARY
One embodiment, accordingly, provides a multi-layer circuit substrate having an integral bus construction that reduces the sensitivity of the impedance to
Teshome Abeye
Wallace, Jr. Douglas Elmer
Dell USA L.P.
Gaffin Jeffrey
Haynes and Boone L.L.P.
Tran Thanh Y.
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