Controlled compliance fine pitch interconnect

Details Controlled compliance fine pitch interconnect Controlled compliance fine pitch interconnect

2002-01-16

2004-12-14

Gushi, Ross (Department: 2833)

Electrical connectors

Preformed panel circuit arrangement, e.g., pcb, icm, dip,...

With provision to conduct electricity from panel circuit to...

Reexamination Certificate

active

06830460

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to a method and apparatus for achieving a very fine pitch, solderless interconnect between a flexible circuit member and another circuit member, and to an electrical interconnect assembly for forming a solderless interconnection with another circuit member.
BACKGROUND OF THE INVENTION
It is desirable to probe test each die or device under test (DUT) before the wafer is cut into individual intergrated circuit die or before packaging. Die testing often needs to be performed at high speed or high frequency, for example 100 MHz data rate or higher. The probe cards that support a plurality of probe needles must provide reliable electrical contact with the bonding pads of the DUT. The shank of the probe needle is typically 0.005 inches to 0.010 inches in diameter.
One test probe technique is known as the Cobra system, in which the upper ends of the probe needles are guided through a rigid layer of an insulating material. The upper ends of the individual probe needles are electrically connected to suitable conductors of an interface assembly that is connected to an electrical test system. Each of the needles is curved and the lower ends pass through a corresponding clearance hole in a lower rigid layer or template of insulating material. The bottom ends of the needles contact the bonding pads on the wafer being tested. The length of the probe needles can result undesirable levels of ground noise and power supply noise to the DUT. Additionally, the epoxy or plastic rigid layers have large coefficients of thermal expansion and cause errors in the positioning of the needle probes.
Another draw-back of current test probe technology is that it can often not accommodate fine pitches. For example, wafer probes typically require a target contact area of about 70 micrometers by 70 micrometers. Flip-chip architecture has terminals on the order of 10 micrometers by 10 micrometers, and hence, can not effectively be tested using wafer probe technology. Consequently, integrated circuits in flip-chip architectures can generally be tested only after packaging is completed. The inability to wafer probe integrated circuits used in flip-chip architecture results in production time delays, poor yields and a resultant higher cost.
Many of the problems encountered in testing electrical devices also occur in connecting integrated circuit devices to larger circuit assemblies, such as printed circuit boards or multi-chip modules. The current trend in connector design for those connectors utilized in the computer field is to provide both high density and high reliability connectors between various circuit devices. High reliability for such connections is essential due to potential system failure caused by misconnection of devices. Further, to assure effective repair, upgrade, testing and/or replacement of various components, such as connectors, cards, chips, boards, and modules, it is highly desirable that such connections be separable and reconnectable in the final product.
Pin-type connectors soldered into plated through holes or vias are among the most commonly used in the industry today. Pins on the connector body are inserted through plated holes or vias on a printed circuit board and soldered in place using conventional means. Another connector or a packaged semiconductor device is then inserted and retained by the connector body by mechanical interference or friction. The tin lead alloy solder and associated chemicals used throughout the process of soldering these connectors to the printed circuit board have come under increased scrutiny due to their environmental impact. Additionally, the plastic housings of these connectors undergo a significant amount of thermal activity during the soldering process, which stresses the component and threatens reliability.
The soldered contacts on the connector body are typically the means of supporting the device being interfaced by the connector and are subject to fatigue, stress deformation, solder bridging, and co-planarity errors, potentially causing premature failure or loss of continuity. In particular, as the mating connector or semiconductor device is inserted and removed from the present connector, the elastic limit on the contacts soldered to the circuit board may be exceeded causing a loss of continuity. These connectors are typically not reliable for more than a few insertions and removals of devices. These devices also have a relatively long electrical length that can degrade system performance, especially for high frequency or low power components. The pitch or separation between adjacent device leads that can be produced using these connectors is also limited due to the risk of shorting.
Another electrical interconnection method is known as wire bonding, which involves the mechanical or thermal compression of a soft metal wire, such as gold, from one circuit to another. Such bonding, however, does not lend itself readily to high-density connections because of possible wire breakage and accompanying mechanical difficulties in wire handling.
An alternate electrical interconnection technique involves placement of solder balls or the like between respective circuit elements. The solder is reflown to form the electrical interconnection. While this technique has proven successful in providing high-density interconnections for various structures, this technique does not facilitate separation and subsequent reconnection of the circuit members.
An elastomer having a plurality of conductive paths has also been used as an interconnection device. The conductive elements embedded in the elastomeric sheet provide an electrical connection between two opposing terminals brought into contact with the elastomeric sheet. The elastomeric material must be compressed to achieve and maintain an electrical connection, requiring a relatively high force per contact to achieve adequate electrical connection, exacerbating non-planarity between mating surfaces. Location of the conductive elements is generally not controllable. Elastomeric connectors may also exhibit a relatively high electrical resistance through the interconnection between the associated circuit elements. The interconnection with the circuit elements can be sensitive to dust, debris, oxidation, temperature fluctuations, vibration, and other environmental elements that may adversely affect the connection.
The problems associated with connector design are multiplied when multiple integrated circuit devices are packaged together in functional groups. The traditional way is to solder the components to a printed circuit board, flex circuit, or ceramic substrate in either a bare die silicon integrated circuit form or packaged form. Multi-chip modules, ball grids, array packaging, and chip scale packaging have evolved to allow multiple integrated circuit devices to be interconnected in a group.
One of the major issues regarding these technologies is the difficulty in soldering the components, while ensuring that reject conditions do not exist. Many of these devices rely on balls of solder attached to the underside of the integrated circuit device which is then reflown to connect with surface mount pads of the printed circuit board, flex circuit, or ceramic substrate. In some circumstances, these joints are generally not very reliable or easy to inspect for defects. The process to remove and repair a damaged or defective device is costly and many times results in unusable electronic components and damage to other components in the functional group.
Multi-chip modules have had slow acceptance in the industry due to the lack of large scale known good die for integrated circuits that have been tested and burned-in at the silicon level. These dies are then mounted to a substrate which interconnect several components. As the number of devices increases, the probability of failure increases dramatically. With the chance of one device failing in some way and effective means of repairing or replacing currently unavailable, yield rates have been low and the manufacturing

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